Design of vehicle information line controller based on SOPC

introduction

MVB (Multi-function Vehicle Bus) based on distributed control is the recommended solution of IEC61375-1 (1999) TCN (International Standard for Train Communication Network). The train communication bus formed by it and WTB (Wire Train Bus) has the characteristics of strong real-time performance and high reliability. MVB, as a fast process control optimized bus, can provide the best response speed. It is a serial data communication bus mainly used for interconnected devices with interoperability and interchangeability requirements. It is suitable for use as a vehicle bus. For fixed-formation trains, MVB can also be used as a train bus, as shown in Figure 1.

As system integration technology continues to mature, a new industry has emerged, namely IP (Intellectual Property) products and modular design. In integrated circuit design, IP specifically refers to circuit modules that can be circulated among design companies through intellectual property trade to achieve specific functions. The essential feature of IP cores is usability. They usually meet the three basic characteristics of good versatility, portability and absolute correctness. They are the core of future SOPC (System On Programmable Chip) design. To make SOPC design successful, more intellectual property (IP) reuse should be used to quickly complete the design and obtain low-cost silicon devices to meet market demand.

The author has conducted an in-depth study on the traditional foreign MVB communication controller chip MVBC and the MVB underlying communication protocol. On this basis, he designed an MVB bus access IP core with independent intellectual property rights and designed an MVB controller using SOPC technology.

1 Introduction to MVBC

MVBC (Multi-function Vehicle Bus Controller) is a new generation of core processor on the MVB bus. It is independent of the physical layer and functional devices, and provides communication interfaces and communication services for each device on the bus. Compared with the previous generation MVB communication controller BAP15-2/3, MVBC has greatly improved in performance and is currently the most advanced communication controller on the MVH bus. The internal structure of MVBC is shown in Figure 2.

MVBC is used to convert serial bit signals from the MVB bus into parallel data bytes, and send the bytes to be sent to the transmission medium through the serialization circuit, realize data processing of the data link layer and part of the transmission layer, and interact with the upper layer software through the communication memory. The bus controller contains the codec circuit and the logic circuit required to control the communication memory, which is used to control the sending and receiving of frames (such as conflict detection, frame leading bit processing and CRC check bit processing, etc.).

2 Implementation of MVB bus access IP core

The bus access IP core is used to replace the MVBC chip of the existing MVB network card to realize the application function. The IP core combines the bus transceiver of the physical layer to complete the bus access. The bus access IP core can be divided into three parts: the physical layer, the data link layer and the interface with the application layer.

① Physical layer: implement baseband Manchester Biphase-L encoding and decoding, media redundancy processing, media installation unit interface, and design of digital phase-locked loop for input decoding.

②Data link layer: including addressing method, F-code (function code) generation, filling of master and slave device frame content, and media access control (MAC), etc.

③ Interface with the application layer: usually adopts the shared memory method, which requires the definition and maintenance of ports, control of communication memory, etc. Its logic block diagram is shown in Figure 3.

2.1 MVB frame structure

There are two frame formats in MVB: one is the master frame that can only be sent by the bus master, referred to as the "master frame"; the other is the slave frame that is sent by the slave in response to the master frame, referred to as the "slave frame". A frame starts with a 9-bit delimiter. The master frame delimiter and the slave frame delimiter are different to prevent synchronization failure. Figure 4 is a diagram of the MVB master-slave frame structure.

2.2 MVB frame transmitter

The MVB bus data is based on frames, and the data frames are transmitted using Manchester code. The encoder and decoder not only perform Manchester encoding and decoding, but also special encoding and decoding of the frame header and frame tail. The traditional Manchester codec will not be able to complete this task. In this design, the method of encoding and decoding is combined with the specific state of the transceiver state machine to solve this problem. The MVB frame transmitter calls the Manchester encoding and CRC check module and the communication storage unit module through the control logic module to complete the transmission of the buffer data.

The design of the transmitter's state machine FSM (Finite State Machine) is described below. One of the main functions of the transmitter is to realize parallel-to-serial conversion and framing. The MVB bus data starts to send data after receiving the send set signal; when the data is stored in the communication storage unit, it waits for the set signal of the control logic module; then it enters the frame sending state, completes the transfer between various states through the triggering of the clock signal, and realizes a set of valid frame data transmission. The transmitter's state machine FSM is shown in Figure 5.

2.3 MVB frame receiver

[page]The key to the receiver is the recognition of valid data frames. The implementation idea is similar to that of the transmitter, and it can be realized based on the coding check. Another problem is the interface method with the bus. This design uses 8-bit parallel data width output, and the method of adding sequence number identification can receive valid data of any given length. The state machine of the receiver is shown in Figure 6.

2.4 Avalon Bus Interface

The Avalon interactive system-on-chip bus developed by Altera is used as the internal bus of this bus access IP core to connect various modules in the IP core. As shown in Figure 7, the bus access IP core structure includes: encoder module, decoder module, sink port refresh time monitoring module, and a class of device logic control module. There are 4 Avalon slave ports in the bus access IP core, among which an Avalon bus master port is set on the NiosII main controller, and Avalon bus slave ports are set on other modules. The main controller controls the data flow transmission on the bus to realize the coordinated work of various modules. Its logic block diagram is shown in Figure 7.

3 SOPC System-on-Chip MVB Controller Design

3.1 Bus Access IP Core and Nios II System Integration

Using QuartersII SOPC Builder tool, a 32-bit NiosII soft-core processor, 4 KB on-chip RAM, MVB bus access IP core (including encoder and decoder) and LCD control module are integrated to form a chip system that can realize MVB-type network node functions on Altera's CycloneII FPGA, as shown in Figure 8. Figure 9 shows the use of various functional modules in SOPCBuilder.

3.2 Software Design on NiosII Processor

Based on the above SOPC system, a basic MVB node is designed to realize process data transmission. The node sets the 0x14 address as the source port. When the master frame polls the 0x14 address, this node packs the data in this port into a slave frame and sends it to the bus to refresh the sink port of the 0x14 address.

The design of the MVB module header file altera_avalon_mvb.h includes the macro definitions for bus access to IP core registers for reading and writing.

In the main function, the MVB bus receiving enable bit is set, and the loop waits for receiving the main frame sent by the MVB main controller. After the node receives the main frame, the program enters the interrupt handler. In the interrupt program, the port address in the received main frame is extracted and compared with the preset port address code. If the address code matches, the node sends the data of this port to the bus through the MVB transmitter to implement the port data refresh operation.

Main loop code excerpt:

4 Simulation and Measured Waveforms

4.1 Simulation waveform

In this experiment, the MVB board designed by the laboratory was functionally simulated and FPGA verified. The MVB system built was verified by sending and receiving process data. The simulation results of the master-slave frame sending process of the MVB bus controller are shown in Figure 10. The master-slave frame data sent are all 0x0055, including 1 frame header and 8-bit CRC check data.

4.2 Measured waveform

After the program is compiled, compile the QuartersII project file again and download the obtained .pof file to the FPGA. After powering on, use an oscilloscope to measure the output pin, and you can observe the MVB frame waveform. The measured waveform is shown in Figure 11. Compared with the IEC-61375 protocol standard, it can be judged that the waveform is a correct waveform that meets the standard, and the source port node receives the correct data, which proves that the process data port is successfully refreshed.

Conclusion

At present, the MVB controller has realized the correct reception and transmission of process variables in the laboratory environment. The functions realized by this bus access IP core are equivalent to those of MVBC, but due to the use of advanced SOPC design technology, its architecture is greatly simplified, the design difficulty is greatly reduced, and the versatility is greatly improved.