Methods for reducing RF power in W-CDMA mobile phones

JasonYoo

Methods for reducing RF power in W-CDMA mobile phones [Copy link]

The spread spectrum wireless communication standard IS-95/3GPP has strict regulations on linearity and adjacent channel power ratio (ACPR). To meet the requirements, high-linearity Class A or Class AB RF power amplifiers are required in wideband code division multiple access (W-CDMA) wireless phones. However, at an output power of +28dBm, the power added efficiency (PAE) of this type of power amplifier is only about 35% at most; if the output power is reduced, the PAE value is even lower.

The power amplifier does not work continuously in talk mode. When the phone user is not talking, the power amplifier will work at half rate (50% working time) or 1/8 rate, so there is no need to worry about the phone heating up in talk mode. However, in data mode, the power amplifier will continue to work until the data transmission is completed. The low efficiency and continuous operation of the power amplifier will quickly drain the battery, and the resulting internal power consumption will also cause the phone to overheat.

Power consumption was a major challenge for early W-CDMA cell phones supporting high-speed data services. It forced designers to use larger heat sinks, more cooling airflow, and larger batteries. Fortunately, over the past few years, these issues have been alleviated as power amplifiers used in CDMA and W-CDMA cell phones have made significant advances in power efficiency.

In CDMA and W-CDMA systems, the RF power output of the power amplifier is not always maximized. To optimize cellular capacity (the number of transmission channels that the base station can handle simultaneously), each handset controls its own RF output power so that the effective signal-to-noise ratio level received by the base station is the same for each handset.

From the probability distribution of RF output power levels of many mobile phones in a specific area, we can know that the average output power of a standard CDMA or W-CDMA mobile phone is: about +10dBm in the suburbs; about +5dBm in the city. Therefore, an effective goal for improving power amplifier efficiency is not the maximum power level, but to find a suitable range between +5dBm and +10dBm.

CDMA and W-CDMA power amplifiers require two supply voltages (see figure). VREF provides bias for the internal driver and power amplifier stages, while VCC is used to bias the driver and power amplifier collectors. By adjusting these two voltages, designers can reduce the power amplifier supply current.

When the RF transmission power is zero, the power amplifier will automatically pull the quiescent current to 100mA (typical value), and at this time VREF and VCC are 3V and 3.4V respectively. Reducing VREF from 3V to 2.9V can reduce the quiescent current by about 20mA.

F1: The design of CDMA/W-CDMA mobile phone power amplifier requires two
supply voltages: Vref and Vcc. The operating current of the power amplifier can be reduced by adjusting these two voltages
.

Therefore, designers can reduce the quiescent current of the power amplifier to a great extent by lowering VREF, but they must ensure that the linearity and ACPR of the power amplifier are not lower than the specification requirements.

Reduce VREF and VCC

If we have an empirical value and can provide the minimum VREF voltage required according to the different output power levels of the power amplifier, we can actively combine VREF control with the power control process of the amplifier. If this method is too difficult, we can simply adjust VREF in two stages, corresponding to low power mode (less than 10dBm) and high power mode (greater than 10dBm).

To adjust VREF through the baseband-controlled D/A converter, a low-power operational amplifier with large output current capability and external gain adjustment is selected.

In a typical wireless handset, the VCC of the power amplifier is taken directly from a single-cell lithium-ion battery, so the operating range of VCC is between 3.2 V and 4.2 V. As mentioned above, statistics show that the power amplifiers of CDMA and W-CDMA operate at a power level of +5 to +10 dBm most of the time.

To this extent, the designer can significantly reduce VCC without sacrificing PA linearity, while reducing power dissipation due to excessive collector bias.

Experimental tests at low power levels showed that we could maintain normal communication with the base station when the collector bias was kept below 0.6V.

A specially designed high efficiency dc/dc buck converter provides a variable bias voltage for the PA collector.

A dedicated digital-to-analog converter output from the baseband processor can be used to adjust the output voltage of the buck converter.

The dc/dc converter that controls the collector voltage of the power amplifier must be able to respond quickly to the control signal. Typically, within 30 microseconds after the analog control level from the baseband processor changes, the output voltage of the dc/dc converter should be stable within 90% of the new set voltage value.

The converter chip provides the appropriate internal gain between its VCC control input and the output voltage that biases the collector of the power amplifier. It also switches at a high frequency to reduce the size of the inductor.

Connecting a dc/dc converter between the power amplifier and the battery highlights a problem, which is the need for high RF power at low battery voltage. In order to provide +28dBm RF power while maintaining the linearity specifications of the power amplifier, manufacturers recommend a minimum VCC of 3.4V. In order to maintain a PAE of 35% at 3.4V, we also need a power amplifier collector current of up to 530mA.

+28dBm RF power: 102.8 mW = 631mW

Required PA power (VCC ICC): 631mW/(PAE/100)?1,803mW.

At VCC = 3.4V, the required power amplifier current (ICC) is: ICC = 1,803mW/3.4V = 530mA.

To support 3.4V VCC and 530mA ICC, the dc/dc converter that powers the power amplifier requires a certain input-output margin.

For example, if the on-resistance of the converter's internal P-channel MOSFET (PFET) is 0.4Ω and the inductor impedance is 0.1Ω, then the series voltage drop across these two components is (0.4Ω+0.1Ω) 530mA = 265mV. Therefore, when the battery voltage is below 3.665V, the dc/dc converter cannot support a 3.4V output.

When the battery voltage is lower than 3.665V, it is best to short the collector of the power amplifier to the battery. Otherwise, the power of the lithium-ion battery cannot be fully utilized.

The usual solution is to bypass the inductor and the internal PFET by connecting a low Rds PFET in parallel. This bypass FRET (which can be built-in or external) connects the battery voltage directly to the collector of the power amplifier in high power mode. This bypass method must be used to meet both high RF power and low battery voltage.

Optimized PAE

The best approach to optimizing PAE is to continuously adjust the bias voltage at the collector of the power amplifier. However, this approach requires factory calibration and complex software to ensure good PA linearity and ACPR when the collector bias voltage is continuously varied. The next best approach is to make step adjustments to the collector bias voltage, usually in two to four steps.

For example, in a fourth-order system, the VCC values included might be: Vbatt, 1.5 V, 1 V, and 0.6 V. The overall efficiency of this system is nearly comparable to that of a system that continuously controls the PA collector bias, and at low or medium power levels, the inductor only needs to deliver less than 150 mA of peak current.

By Jay Kim
Application Engineer
Maxim Integrated Products

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