for loop simulation problem

chenbingjy

for loop simulation problem [Copy link]

 

My testbench simulation file is as follows:

`timescale 1 ns/ 1 ps
module LAMP_vlg_tst();
// constants                                           
// general purpose registers
reg eachvec;
// test vector input registers
reg clk;
reg rst_n;
// wires                                               
wire led;

// assign statements (if any)                          
LAMP i1 (
// port map - connection between master ports and signals/registers   
	.clk(clk),
	.led(led),
	.rst_n(rst_n)
);


reg [7:0] memory [0:255];

integer scan; 
integer index=3;


initial begin
	clk=0;
	#10 clk=~clk;

end 

initial begin

$readmemh("memory.list", memory);

end
if(index>0)
	begin
		for(scan=0;scan<index;scan=scan+1)
			if(memory[scan]>0)
				begin
					$display("%d",memory[scan]);
				end
	end
else
			$display("error--indexiszero");
endmodule

But the simulation fails, prompting

Please help me solve this problem, thank you!

lugl4313820

I looked at your error message:

Is it true that the variable declaration of scan cannot be integer?

Modified to genvar.

chenbingjy

lugl4313820 posted on 2022-10-8 08:51 I looked at your error message: The variable declaration of scan cannot be integer; change it to genvar.

Thanks!

I changed it to the following:

`timescale 1 ns/ 1 ps
module LAMP_vlg_tst();
// constants                                           
// general purpose registers
reg eachvec;
// test vector input registers
reg clk;
reg rst_n;
// wires                                               
wire led;

// assign statements (if any)                          
LAMP i1 (
// port map - connection between master ports and signals/registers   
	.clk(clk),
	.led(led),
	.rst_n(rst_n)
);



reg [7:0] memory [0:255];

genvar scan; 
parameter index=3;

initial begin
	clk=0;
	#10 clk=~clk;

end 

initial begin

$readmemh("memory.list", memory);


if(index>0)
	begin
		
		for(scan=0;scan<index;scan=scan+1)
			begin
			if(memory[scan]>0)
				
					$display("%d",memory[scan]);
					memory[scan]=0;
				end
			
		end
		
	
else
			$display("error--indexiszero");

end
endmodule

Running it prompts an error:

lugl4313820

You can use Baidu or Yingbi to search and report the error information, so that you can solve the problem yourself later. I don’t have your development environment and it’s difficult to do testing, but the method to solve the problem is the same.

chenbingjy

So I continued to change:

`timescale 1 ns/ 1 ps
module LAMP_vlg_tst();
// constants                                           
// general purpose registers
reg eachvec;
// test vector input registers
reg clk;
reg rst_n;
// wires                                               
wire led;

// assign statements (if any)                          
LAMP i1 (
// port map - connection between master ports and signals/registers   
	.clk(clk),
	.led(led),
	.rst_n(rst_n)
);



reg [7:0] memory [0:255];

genvar scan; 
parameter index=3;

initial begin
	clk=0;
	#10 clk=~clk;

end 

initial begin

$readmemh("memory.list", memory);


if(index>0)
	begin
		generate
		for(scan=0;scan<index;scan=scan+1)
			
			if(memory[scan]>0)
				begin
					$display("%d",memory[scan]);
					memory[scan]=0;
				end
				
		endgenerate	
		end
		
	
else
			$display("error--indexiszero");

end
endmodule

Another error message:

Please help me, I am at my wits' end. Thank you!

chenbingjy

lugl4313820 posted on 2022-10-8 09:43 You can use Baidu or Yingbi to search and report the error information, so that you can solve the problem yourself in the future. I don’t have your development environment around me, and it’s not easy to do testing...

Thank you! Some error messages cannot be found at all

lugl4313820

chenbingjy posted on 2022-10-8 09:49 Thank you! Some error messages cannot be found at all

I looked at the English error message and found that scan can only be used in for. Is it possible to add another parameter to replace memory[scan]?

chenbingjy

lugl4313820 posted on 2022-10-8 11:48 I looked at the English error message and found that scan can only be used in for. Should we add another parameter to replace memory[scan]

Thanks!

I changed it to the following:

`timescale 1 ns/ 1 ps
module LAMP_vlg_tst();
// constants                                           
// general purpose registers
reg eachvec;
// test vector input registers
reg clk;
reg rst_n;
// wires                                               
wire led;

// assign statements (if any)                          
LAMP i1 (
// port map - connection between master ports and signals/registers   
	.clk(clk),
	.led(led),
	.rst_n(rst_n)
);



reg [7:0] memory [0:255];
reg [7:0] a;

parameter index=3;
genvar scan; 


initial begin

$readmemh("memory.list", memory);


if(index>0)
	begin
	
		
		for(scan=0;scan<index;scan=scan+1)
		
			a=memory[scan];
			if(a>0)
				begin
					$display("%d",a);
					a=0;
				end
		
			
		end
		
	
else
			$display("error--indexiszero");

end
endmodule

Simulation error:

# ** Error: D:/CCB/CPLD/study/FIVE/simulation/modelsim/LAMP.vt(64): Invalid context for genvar scan. A genvar can be used only inside of the generate loop that it indexes.
# ** Error: D:/CCB/CPLD/study/FIVE/simulation/modelsim/LAMP.vt(64): Invalid context for genvar scan. A genvar can be used only inside of the generate loop that it indexes.
# ** Error: D:/CCB/CPLD/study/FIVE/simulation/modelsim/LAMP.vt(64): Invalid context for genvar scan. A genvar can be used only inside of the generate loop that it indexes.
# ** Error: D:/CCB/CPLD/study/FIVE/simulation/modelsim/LAMP.vt(64): Invalid context for genvar scan. A genvar can be used only inside of the generate loop that it indexes.
# ** Error: D:/CCB/CPLD/study/FIVE/simulation/modelsim/LAMP.vt(66): Invalid context for genvar scan. A genvar can be used only inside of the generate loop that it indexes.

It seems that you need to use the generate statement

So I changed it to the following:

`timescale 1 ns/ 1 ps
module LAMP_vlg_tst();
// constants                                           
// general purpose registers
reg eachvec;
// test vector input registers
reg clk;
reg rst_n;
// wires                                               
wire led;

// assign statements (if any)                          
LAMP i1 (
// port map - connection between master ports and signals/registers   
	.clk(clk),
	.led(led),
	.rst_n(rst_n)
);



reg [7:0] memory [0:255];
reg [7:0] a;

parameter index=3;
genvar scan; 


initial begin

$readmemh("memory.list", memory);


if(index>0)
	begin
	
		generate
		for(scan=0;scan<index;scan=scan+1)
		
			a=memory[scan];
			if(a>0)
				begin
					$display("%d",a);
					a=0;
				end
		
		endgenerate	
		end
		
	
else
			$display("error--indexiszero");

end
endmodule

Another error message:

# ** Error: (vlog-13069) D:/CCB/CPLD/study/FIVE/simulation/modelsim/LAMP.vt(63): near "generate": syntax error, unexpected generate.
# ** Error: (vlog-13069) D:/CCB/CPLD/study/FIVE/simulation/modelsim/LAMP.vt(64): near ")": syntax error, unexpected ')', expecting ';'.
# ** Error: (vlog-13069) D:/CCB/CPLD/study/FIVE/simulation/modelsim/LAMP.vt(73): near "endgenerate": syntax error, unexpected endgenerate.

It seems that for loops don't work well with if statements. It's really frustrating.

chenbingjy

I simplified it again. The code is as follows:

`timescale 1 ns/ 1 ps
module LAMP_vlg_tst();
// constants                                           
// general purpose registers
reg eachvec;
// test vector input registers
reg clk;
reg rst_n;
// wires                                               
wire led;

// assign statements (if any)                          
LAMP i1 (
// port map - connection between master ports and signals/registers   
	.clk(clk),
	.led(led),
	.rst_n(rst_n)
);



wire [7:0] memory [15:0];


parameter index=3;
genvar scan; 

initial begin

$readmemh("memory.list", memory);
end


	generate
	for(scan=0;scan<index;scan=scan+1)
		
			
			if(memory[scan]>0)
				begin
					$display("...");
					
				end
		
		endgenerate	
	
endmodule

Still wrong:

Tip: unexpected '$display'

Can't the $display function be used here? Thanks

lugl4313820

chenbingjy posted on 2022-10-8 14:02 I simplified it again. The code is as follows: `timescale 1 ns/ 1 ps module LAMP_vlg_tst(); // constants ...

What language is this? Is it because the for is not closed, so it reports an error? Check whether the for is closed in pairs?

chenbingjy

lugl4313820 posted on 2022-10-8 15:21 What language is this? Is it because for is not closed, so it reports an error? Check if the for is closed in pairs?

Feeling closed off

lugl4313820

chenbingjy posted on 2022-10-8 19:36 Feeling closed

If there is a problem with the format, you can copy a typical example from someone else and compare it with your own grammar. This way you can find out where the problem lies and improve yourself. Or you can take a look at this basic grammar course first. This way you can solve the problem faster.

chenbingjy

lugl4313820 posted on 2022-10-9 09:32 Is there a problem with the format? Copy a typical example from someone else and compare it with your own grammar. This way you can find out the problem and improve yourself...

Thank you! The for loop alone is fine, but adding the if else statement does not work.