The vivado simulation output waveform signal input is all Z and the output is all X

1nnocent

The vivado simulation output waveform signal input is all Z and the output is all X [Copy link]

Source file:

`timescale 1ns / 1ps
module clk_counter(
    input               sys_clk,
    input               rst_n,
    input               gate,
    output reg[31:0]       clk_cnt,
    output reg          counter_valid
    );
    always@(posedge sys_clk or negedge rst_n)
    begin
        if(rst_n == 1'b0)
            begin
                clk_cnt <= 32'd0;
                counter_valid <= 1'b0;
            end
        else if(gate == 1'b1)
            begin
                clk_cnt <= clk_cnt + 32'd1;
            end
        else if(gate == 1'b0)
            begin
                counter_valid <= 1'b1;
            end
    end
endmodule

Simulation stimulus file:

`timescale 1ns / 1ps
module vtf_clk_counter;
    //inputs
    reg               clk;
    reg               rst_n;
    reg               gate;   
    //outputs 
    wire[31:0]       clk_cnt;    
    wire          counter_valid;
    
    clk_counter uut(
        .sys_clk(clk),
        .rst_n(rst_n),
        .gate(gate),
        .clk_cnt(clk_cnt),
        .counter_valid(counter_valid)
    );
    initial begin
        clk = 0;
        rst_n = 0;
        gate = 0;
        #100;
            rst_n = 1;
        #100;
            gate = 1;
        #1000;
            gate = 0;
    end
    always #25 clk = ~clk;
endmodule

Simulation waveform:

What is the problem with this simulation waveform?

1nnocent

The input and output signals are all defined, and initial values are assigned to the signals, but there is nothing in the simulation waveform.

chenzhufly

There is no problem with the file. Let’s enlarge the waveform and see. The current time scale is ms, which is too big.

1nnocent

chenzhufly published on 2022-6-7 10:45 There is no problem with the file. Let’s enlarge the waveform and see. The current time scale is ms, which is too big.

OK, thanks, the problem has been solved

chenzhufly

1nnocent published on 2022-6-11 14:28 OK, thank you, the problem has been solved

If you solve it, please tell me how you solved it, so that others who encounter the same problem can learn from it.

1nnocent

chenzhufly published on 2022-6-13 11:15 If you solve it, please tell me how you solved it, so that others who encounter the same problem can learn from it

You posted the simulation picture and said it was fine, thinking that you were careless and didn't adjust the timeline.

I forgot about it now. It seems that when the top-level module calls this module, the parameter bit width does not correspond well, and the 32-bit clk_count[31:0] is passed to one bit width.

chenshea

It may be that the simulation file was not added to the project.