Gaoyun FPGA uses the remaining DDR pin usage issues

littleshrimp

Gaoyun FPGA uses the remaining DDR pin usage issues [Copy link]

 

In the early Gaoyun DDR design reference manual Gaoyun FPGA DDR3 design reference manual , if the FPGA uses 1:4 mode and one pin of a differential pair is used as DDR, the other pin can only be used for simple input, such as a button or switch.

Due to the pin resource problem, I hope to use the unused pins for high-speed input, such as 100MHz input. In order to confirm this problem, I called Gaoyun technical support on December 27. After confirmation, they replied that it can only be used for buttons, and the 100MHz input is too high. They suggested that I use the GW5A model, saying that the 25K is more cost-effective than the 18K, and there is no pin problem.

However, when I checked this document on the official website today, I found that the corresponding introduction was gone and the document was updated on December 28.

The corresponding introduction becomes as shown in the figure below, removing the description that the pin can only be used as input. It seems that it can be understood that it can be used for both input and output, as long as it is not used on DDR.

haocede

I am here to mine. I am interested in this post and want to learn it. It would be nice if there is a more detailed explanation, such as what the pin output signal is used for. I am a novice and don't understand it. Please don't laugh at me if the description is inaccurate.

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