Evaluation of the domestic FPGA Gaoyun GW1N-4 series development board - Hardware Part 1

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Evaluation of the domestic FPGA Gaoyun GW1N-4 series development board - Hardware Part 1 [Copy link]

 

As a hardware engineer, the development of FPGA systems is a great test of an engineer's control over hardware resources. As the saying goes, knowing yourself and your enemy means winning every battle. To fully tap the potential of an FPGA and maximize the power of its hardware resources, you must have a comprehensive understanding of it. In general, you should follow the principle of from hard to soft, from inside to outside, and from top to bottom. In the next article, we will first conduct a comprehensive study of its hardware.

Hardware - Overall Overview:

The overall layout of the DK_MINI_GW1N-LV4LQ144C6I5_V1.1 development board is a very reasonable development board. Compared with the Zynq development board of Mil that I used before, the peripherals are much richer. The development board is mainly composed of FPGA, DC-DC power supply, clock, serial flash, JTAG interface, USB to serial port chip, USB interface, power switch, reset button, digital tube, 16 LEDs, 4 slide switches, 2*8pinGPIO pins, 24pinGPIO pins, 32pinGPIO pins, etc. The interface is relatively rich.

The hardware diagram system block diagram is as follows:

Hardware: GW1N-4K-LQFP144:

Download the schematics and user manual from the bottom of the event page. Through the relevant links in the manual, we can visit Gaoyun's official website. We can see that Gaoyun is a high-tech company specializing in domestic FPGAs. The company currently has three series of products. The chip we are studying today is the first generation of the Little Bee family series. The Little Bee family's products are characterized by low power consumption, instant start, low cost, non-volatility, high security, rich packaging types, and convenient and flexible use. For GW1N-4K-LQFP144, it can be seen from the chip number that GW1N indicates that it is the first generation of the Little Bee family. We can see other members of the family under the product list on the official website. Gaoyun 's FPGA products are based on the 55nm process. For comparison, I compared the XILINX spartan-6 series product xc6slx4 with the 45nm process.

It can be seen that compared with the XILINX product of the same level, the GW1N-4K-LQFP144, the logic resources are still very good. The Gaoyun GW1NS series also has an embedded ARM Cortex-M3 , similar to the Xilinx Zynq series. It can be seen that domestic FPGAs have indeed taken an important step in the journey of catching up with international giants.

The following are the basic features of the GW1N series FPGA:

From the DK_MINI_GW1N-LV4LQ144C6I5_V1.1 user manual, we can see that GW1N-4K-LQFP144 supports LV version and core voltage supports 1.2v. Lower core voltage means lower power consumption. Through the link of DK_MINI_GW1N-LV4LQ144C6I5_V1.1 user manual, let's take a look at the document DS100 (GW1N series FPGA product data sheet). The document table 2-1 also lists the basic information of the GW1N series FPGA. Our GW1N-4 is packaged in LQFP144 package, thin QFP (Low-profile Quad Flat Package), 1.4mm thick

Let’s take a look at the architecture of GW1N-4 :

Configurable functional units:

Configurable Function Unit (CFU) and Configurable Logic Unit (CLU) are the basic units that make up Gowin FPGA.

Configurable Function Unit (CFU)/Configurable Logic Unit (CLU) = 4*(Configurable Logic Block (CLS) + Configurable Routing Unit (CRU)) = 4*(2*Four-input Look-up Table (LUT)) + 3(2*Register (REG).

The CLU can be configured as a basic lookup table, an arithmetic logic unit, and a read-only memory

CFU can be configured as basic lookup table, arithmetic logic unit, static random access memory, read-only memory

Input and output modules:

IOB is mainly composed of I/O Buffer I/O logic and corresponding wiring resources. Each IOB consists of two I/O pins. These two groups of pins can be configured as a set of differential signals or as two sets of single-ended signals.

Based on the VCCO mechanism of BANK, it supports multiple level standards such as LVCMOS, PCI, LVTTL, LVDS, SSTL, and HSTL, and supports SDR and DDR modes. Each BANK supports independent power supply, with independent power supply Vcco and independent reference voltage Vref. GW1N-4 IO has 4 BANKs

GW1N series FPGA products are divided into LV and UV versions:

The LV version supports 1.2V Vcc power supply to meet the needs of low-power users. Vcco can be set to 1.2V, 1.5V, 1.8V, 2.5V, 3.3V as needed.

The UV version allows users to use a single power supply, with an internal integrated linear regulator, and the core voltage supports 1.8V, 2.5V, and 3.3V

GW1N-4 supports true LVDS output, but does not support internal 100Ω input differential matching resistors. Banks that do not support LVDS output support internal 100Ω input differential matching resistors.

I/O logic;

I/O logic consists of delay module, I/O register, sampling module, etc.

Delay block:

IODELAY is included in each I/O, providing a total of 128 delay steps, with one step delay of approximately 30ps

I/O Registers:

Input register (INFF), output register (OUTFF) and high impedance control register (TCFF)

Sampling module:

IEM is used in DDR mode and contains a simple deserializer (DES) and a serializer (SER) SERDES

I/O logic working mode:

Can be configured as output signal, input signal, INOUT signal and tri-state output signal

Block SRAM module:

Each BSRAM has a capacity of 18Kbits and can be configured as single port mode, dual port mode, semi dual port mode, read-only memory mode, and the clock frequency can reach 190Mhz

User Flash Resources:

GW1N-4 user flash memory resources are 256Kbits, bit width is 32 bits, clock is 40MHz

Digital information processing module (DSP):

DSP resources are very important for algorithm-based projects, such as implementing FIR filters or FFT, which require a large number of DSPs. DSP modules occupy 9 CFUs. Each DSP = 2*macro units = 2* (2*pre-adder + 2*18-bit multiplier + three-input arithmetic logic unit)

Clock resources:

The GW1N series FPGA provides dedicated global clock (GCLK), high-speed clock (HCLK), phase-locked loop (PLL), etc.

Global reset:

Contains a global reset that connects directly to the device's internal logic

Programming configuration:

Supports SRAM programming and Flash programming, of which Flash programming supports both on-chip and off-chip methods, and also supports DUAL BOOT mode, which can back up configuration data to external Flash. In addition to supporting the general JTAG mode, the interface also supports GowinCONFIG configuration mode unique to Gowin Semiconductor.

On-chip crystal oscillator;

The GW1N series FPGA has a built-in programmable crystal oscillator that supports a clock frequency range of 2.5MHz-125MHz with an accuracy of ±5%. The programming process provides a clock source for the MSPI mode. The configuration is a user-designed clock source that can be used to obtain the required clock by setting parameters. The formula for calculating the output clock frequency of the on-chip crystal oscillator of the GW1N-4 device is: fout=210MHz/Param (Param range is an even number from 2 to 128).

Electrical characteristics:

Pay special attention to the core voltage range, which is an important part of the design. The timing parameter part Table 4-24 is also very important. The final timing constraints in engineering design are often the most time-consuming task.

The above is the study of on-chip resources. The next article will unbox and then study off-chip resources.

littleshrimp

Indeed, Gaoyun has many products worth playing with. We can practice with this board first. I bought the GW1NSR board before, but unfortunately the hard-core processor inside was damaged by changing the BANK voltage before I could play with it. I will have to try it again when I have the chance.

打破传统

littleshrimp posted on 2021-12-9 20:10 Indeed, Gaoyun has many products worth playing with. We can practice with this board first. I bought the GW1NSR board before, but unfortunately I haven’t played with it yet...

Generally speaking, if there is a problem with the voltage of only one bank, the other parts of the FPGA can still be used. FPGAs are powered independently. Try disconnecting the broken power supply to see if it can be fixed. However, Gaoyun's UV version seems to be powered by a single power supply. Yours should be the LV version, right?

nmg

This photo is too blurry. Did it become blurry after it was uploaded and inserted?

littleshrimp

Breaking tradition Published on 2021-12-10 09:38 Generally speaking, if there is a problem with the voltage of only one bank, the other parts of the FPGA can still be used. The FPGA is powered independently. Disconnect the broken power supply and try...

I am using a Tang nano 4k board. I want to change the voltage from 3.3v to 2.5v, including the BANK0 corresponding to the emulator and other BANK power supplies are connected together. Before I changed it, I confirmed that the onboard emulator can work at 2.5v. After the change, it worked normally for a while, but later it could not be simulated. I re-soldered the DC-DC feedback resistor that I changed, and it worked normally for a while. Later, when it did not work well, I directly used an external 2.5V power supply, and it worked for a short while and then it completely did not work. Now I feel that the FPGA may not be broken, and the problem may be with the onboard emulator.

打破传统

nmg posted on 2021-12-10 09:44 This photo is too blurry. Did it become blurry after being uploaded and inserted?

It should be. Pasting doesn't work. Do I have to upload the picture directly?

打破传统

nmg posted on 2021-12-10 09:44 This photo is too blurry. Did it become blurry after being uploaded and inserted?

I uploaded a new picture and it's better, but it seems to be blurry.

nmg

Breaking tradition Published on 2021-12-10 11:30 I uploaded a picture again and it’s better, but it seems to be blurry

freebsder

Very detailed, thanks for sharing!