Evaluation of domestic FPGA Gaoyun GW1N-4 series development board - Software Part 3

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Evaluation of domestic FPGA Gaoyun GW1N-4 series development board - Software Part 3 [Copy link]

 

The following is the timing constraints part:

The most important goal in FPGA design is to ensure that the design meets the timing requirements, that is, there are no violations, and then the optimization of power consumption resources, etc. can be seen. The importance of timing constraints to the design can be seen.

The basic probability of timing analysis will not be repeated here. It is mainly based on static timing analysis. Next, let's learn the timing editor provided by Gaoyun Yunyuan software and the timing constraint process.

I still open the sample project counter mentioned in the previous physical constraint chapter, and start the timing constraint editing tool as shown in the figure:

There are also two ways to generate timing constraints. One is to use the timing constraint tool to generate them in a graphical interface in sequence, and the other is to directly edit the generated timing constraint file .SDC file. Let's learn the constraint process below:

1. Clock constraints:

(1) Click the Constraints menu bar or select Clock in the Timing Constraints window and then right-click in the constraint list box, or find the port that needs to be constrained as a clock in the netlist box and right-click to add a clock (main clock constraint). (2) Add constraints directly in the SDC file. The Gaoyun timing constraint syntax specification reference standard is also SDC (Synopsys Design Constraint), which can be said to be the same. The clock constraints are as follows:

①

create_clock[-name<clock_name>]-period <period_value>[-waveform <edge_list>]<objects>[-add]

This constraint is the most important timing constraint. Generally, all designs have this constraint. Another point worth noting is that from this constraint, it can be seen that a port can constrain multiple clocks. The timing analysis tool will treat the first clock as the source clock and the subsequent clocks as the destination clock to generate a report as shown below:

②

create_generated_clock [-name <clock name>]-source <master pin>[-edges <edge list>][-edge_shift <shift list>][-divide_by <factor>][-multiply_by<factor>][-duty_cycle<percent >][-add][-invert][-master_clock <clock>][-phase <phase>][-offset <offset>]<objects>

This constraint is rarely used in general, because the tool will automatically add derived clocks based on the main clock.

③

set_clock_latency -source [-rise | -fall][-late | -early]<delay>[-clock <clock list>]<object list>

This constraint sets the delay before the clock signal reaches the device clock port, so it must be set under clear and specific delay conditions. Generally speaking, the delay is very small and can be basically ignored.

④

set_clock_uncertainty[-from <from clock>][-rise_from <rise from clock>][-fall_from <-fall from clock>][-to <to clock>][-rise_to <rise to clock>][-fall_to <fall to clock>][-setup | -hold]<uncertainty value>

This constraint sets the clock uncertainty to help the tool better analyze the system performance and estimate the stability of the system operation.

⑤

set_clock_groups[-asynchronous | -Exclusive][-group <clock name>]

In order to use this command, we add a clock in the project

This constraint is mainly used to constrain asynchronous clocks (of course, synchronous clocks can also be constrained). This constraint is frequently used in projects with multiple clock paths to prevent tools from performing related timing analysis on asynchronous clocks.

1. I/O delay constraints

(1) Click the Constraints menu bar or select I/O Delay in the Timing Constraints window and right-click in the constraint list box. (2) Add constraints directly in the SDC file. The Gaoyun timing constraint syntax specification reference standard is also SDC (Synopsys Design Constraint), which can be said to be the same. The IO constraints are as follows:

set_input_delay-clockclock_name[-clock_fall][-rise][-fall][-max][-min][add_delay][source_latency_included]

<delay_value><port_list>

set_output_delay-clockclock_name[-clock_fall][-rise][-fall][-max][-min][-add_delay][source_latency_included]<delay_value><port_list>

These two constraints are used to set data delays. They are set when it is clear that the data arrives too early or too late with the clock to ensure the correct latching of data input or output.

1. Timing Path Constraints

(1) Click the Constraints menu bar or right-click in the constraint list box after selecting Path in the Timing Constraints window. (2) Add constraints directly in the SDC file. The Gaoyun timing constraint syntax specification reference standard is also SDC (Synopsys Design Constraint), which can be said to be the same. The timing path constraints are as follows:

set_false_path [-from <from list>][-to <to list>][-through <through list>][-setup][-hold]

set_max_delay (set_min_delay)[-from <from list>][-to <to list>][-through <through_list>]<delay value>set_min_delay[-from <from list>][-to <to list>][- through <through_list>]

set_multicycle_path[-setup|-hold][-start|-end][-from <from_list>][-to <to list>][-through <through_list>]<path multiplier>

Among these constraints, the set_false_path constraint has the same purpose as setting an asynchronous clock group, but the clock group has a higher priority and a command can cover a wider range. The set_max/min_delay limits the delay on certain paths and is used to improve local timing paths. Use it with caution, as it may affect the entire system. set_multicycle_path is a constraint for performing multi-cycle analysis and is rarely used.

1. Working conditions constraints

(1) Click the Constraints menu bar or right-click in the constraint list box after selecting Path in the Timing Constraints window. (2) Add constraints directly in the SDC file. The Gaoyun timing constraint syntax specification reference standard is also SDC (Synopsys Design Constraint), which can be said to be the same. The working condition constraints are as follows:

set_operation_conditions[-grade <c|i|a>][-model <slow|fast>][-speed <speed>][-setup][-hold][-max][-min][-max_min]

This constraint is to set the chip working conditions. The effect of this command is clear when the speed and temperature level of the chip are known.

1. Timing Report Constraints

(1) Click the Constraints menu bar or select Report in the Timing Constraints window and then right-click in the constraint list box. (2) Add constraints directly in the SDC file. The Gaoyun timing constraint syntax specification reference standard is also SDC (Synopsys Design Constraint), which can be said to be the same. I will not repeat the constraints of the timing report. Refer to SUG940. This part of the constraints mainly involves the content of the timing report and does not affect the system. Users can add it as needed. The timing report must be understandable. Let's do a small experiment to see how the timing report reflects the timing violation.

First I constrained the clock to 200M as follows:

It can be seen that the setpu margin of three paths in the report becomes negative, that is, the data demand time is less than the data arrival time. It can be seen that the maximum clock can run at 179.584MHz, which is generally less than this value.

Here I also found that it would be better to add a refresh button to the timing constraint editor, just like the physical constraint editor, so that if I have edited it in the constraint file, I can reload it in the tool. Otherwise, I have to close the editor and reopen it, which is a bit inconvenient.