Evaluation of the domestic FPGA Gaoyun GW1N-4 series development board - Software Part 2

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Evaluation of the domestic FPGA Gaoyun GW1N-4 series development board - Software Part 2 [Copy link]

 

For simple designs, for physical constraints we may only need to bind the pins and levels, and for timing constraints we only need to constrain the main clock to meet the design and timing requirements. However, for more complex designs, physical constraints not only focus on the pin levels but also the specific configuration of the pins, and timing constraints are not just as simple as main clock constraints. There are often timing exceptions, input and output delays, etc. Generally speaking, the final design will often fully consume the resources of the FPGA, which will cause the wiring timing to be very tight. It can be said that most of the time for a design will be spent on adjusting the timing, so physical timing constraints are a very important point in FPGA design. Today we will focus on learning about the physical constraints and timing constraints of Gaoyun software .

First, the physical constraints:

We create a new sample project counter. Here is a suggestion: the new project cannot be opened by default and located in the previous directory. It is very inconvenient to manually locate it again.

module counter1(out, cout, data, load, cin, clk, ce, clko);

output [7:0] out;

output cout;

output clko;

input ce;

input [7:0] data;

input load, cin, clk;

reg [7:0] out;

always @(posedge clk)

begin

if (load)

out = data;

else

out = out + cin;

end

assign cout = &out & cin;

wire clkout;

CLKDIV clkdiv_inst (

.CLKOUT(clkout),

.HCLKIN(clk),

.RESETN(1'b1),

.CALIB(1'b0)

);

defparam clkdiv_inst.DIV_MODE = "2";

defparam clkdiv_inst.GSREN = "false";

DQCE dqce_inst (

.CLKOUT(clko),

.CLKIN(clkout),

.CE(ce)

);

endmodule

The project contains an 8-bit counter, a clock divider primitive instantiation, and a dynamic quadrant clock enable primitive instantiation (we will also discuss these two primitive instantiations in the clock resources section later).

After synthesis, open the FloorPlanner physical constraints editor.

Gaoyun Yunyuan software provides FloorPlanner physical constraint editor, which supports reading, editing and generating new constraint files for I/O, primitive, Group and other attributes and location information. After opening, a physical constraint file .cst will be generated in the project folder.

Gaoyun Yunyuan software does not have many automatic routing strategies like Vivado, and it does not have room for selection. Therefore, in complex designs, timing convergence must be achieved more by adjusting timing and physical constraints (manual routing).

Next, we will learn how to perform physical constraints and the significance of various physical constraints through the study of FloorPlanner.

1. I/O Constraints

Click the IO Constraints edit window. (1) The Location constraint can be combined with the Chip Array window to drag the selected Port to the corresponding position in the Chip Array window. The position can be several ports (the software will eventually select the port with the largest number, which we will verify later). (2) The Location constraint can be directly double-clicked in the Location column behind the Port in the IO Constraints edit window to directly fill in the location to be bound. Multiple locations are separated by English commas. The attribute constraint can be directly modified in the corresponding attribute column behind the Port port. (3) The Location constraint and attribute constraint can also be added directly in the .cst file using the following syntax:

IO_LOC "obj_name" obj_location [exclusive];

IO_LOC "obj_name" obj_location [exclusive];

2. Primitive constraints

Click the Primitive Constraints edit window. (1) Right-click and select Select Primitives. Select the primitive to be constrained in the drop-down list box to constrain its position. You can directly drag to the constraint position in the Chip Array window in the Constraints view state, or directly enter the position in the Locations. (2) Primitive position constraints can also be added directly in the .cst file using the following syntax:

INS_LOC “obj_name” obj_location [exclusive];

3. Primitive group constraints

Click the Group Constraints edit window (1) Right-click New Primitive Group, enter the group name to add group members to add a primitive group constraint. Similarly, right-click New Relative Group, enter the group name to add group members to add a relative group constraint (2) Primitive group constraints and relative position constraints can also be added directly in the .cst file using the following syntax:

GROUP group_name = { “obj_names ” } [exclusive];

GROUP group_name += { “obj_names ” } [exclusive];

GRP_LOC group_name group_location[exclusive];

REL_GROUP group_name = { “obj_names ” };

REL_GROUP group_name += { “obj_names ” };

INS_RLOC “obj_name” relative_location;

The primitive group constraint is to constrain several members to the same absolute position, while the relative position group constraint is to use the member with the smallest position as the relative position origin and the smallest GRID index, and constrain other members to a certain position relative to this origin (the relative displacement is obtained by subtracting the indexes, which is strange to use and not very practical) as shown below:

4. Resource reservation constraints

Click the Resource Reservation edit window (1) Right-click Resource Resources, and in the Chip Array window in the Constraints view, drag the constraint to the location you want to reserve, or edit the location directly in the Locations column (2) Resource reservation location constraints can also be added directly in the .cst file using the following syntax:

LOC_RESERVE location [ res_obj ];

Reserve some resources so that the routing layout is not used. This constraint is still very useful.

5. Global clock distribution constraints

Click the Clock Assignment edit window (1) Right-click Resources, select net, select type, and select signal. (2) Global clock assignment constraints can also be added directly in the .cst file using the following syntax:

CLOCK_LOC "net_name" global_clocks = fanout;

This constraint can route certain important paths to global clock resources, which is very effective for timing convergence.

6. Clock quadrant constraints

Click the Quadrant Constraints edit window (1) Right-click Select Dcs/Dqce, select DCS or DQCE, and then select the quadrant under Position. (2) Clock quadrant constraints can also be added directly in the .cst file using the following syntax:

INS_LOC "obj_name" quadrant;

This constraint mainly constrains the quadrant of the dynamic clock controller primitive.

7. High-speed clock constraints

Click the Hclk Constraints edit window (1) Right-click Select Hclk, select DCS, and then select the position under Position (2) High-speed clock constraints can also be added directly in the .cst file using the following syntax:

INS_LOC “obj_name” location;

This constraint is mainly for CLKDIV, DLLDLY constraints to the relevant position

8. Reference voltage constraints

Click the Vref Constraints edit window (1) Right-click Define Vref Driver, drag to the reference port position in the Constraints view of the Chip Array view or directly edit the corresponding position in the Locations column (2) The reference voltage constraint can also be added directly in the .cst file using the following syntax:

USE_VREF_DRIVER vref_name [location];

This constraint is used to select the external reference voltage for each bank. It is not usually used.

The above is the content of Gaoyun Yunyuan software physical constraints. Of course, these constraints are not necessarily all required in the design. There are also appropriate additions to match the timing constraint convergence and power consumption. In the next article, we will continue to learn the timing constraint part

The following demonstrates which IO the software will eventually choose when the port is constrained to several IOs:

Fred_1977

The author of this thread has spent quite a lot of time on this and is quite attentive. I am not a software developer, but I still want to support you!

打破传统

Fred_1977 posted on 2021-12-26 11:22 The OP spent a lot of time on this, and it's quite attentive. I'm not a software developer, but I still want to support you!

Thank you! Nothing, just a study note