On-chip memory resources of RSL10

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On-chip memory resources of RSL10 [Copy link]

 

　　There are two processors inside RSL10, in addition to the main ARM Cortex-m3, there is also a dedicated LPDSP32. The two processors have their own dedicated memory for running programs, and also have a common data memory.

The ARM Cortex-M3 we are familiar with has three buses. The space below address 0x20000000 is accessed through the I-Code or D-Code bus, which is suitable for running programs and data storage. The S bus is used to access hardware devices, including system memory that can be accessed by DMA. In RSL10, all memories can be accessed by Cortex-M3, but LPDSP32 cannot access the Cortex-M3's private Boot ROM, Flash, NVR and program RAM. The DMA controller cannot access the program storage memory of Cortex-M3 and LPDSP32. Because multiple bus masters may access a certain block of memory at the same time, there are multiple arbiters in the bus structure to solve the problem of bus contention.

　　In fact, the RAM in the block diagram above is divided into many small blocks. For example, the Data RAM is three 8kB SRAMs. The advantages of dividing into multiple blocks are: (1) Different blocks can be accessed by different bus masters at the same time. (2) Unused blocks can be turned off to reduce power consumption.

The Flash used for code storage is 384kB, starting from address 0x100000, which is something to pay attention to when developing software. The SRAM for program data and stack can be located at 0x20000000, or at 0x200000 (32kB).

　　According to the manual, after RSL10 is powered on and reset, it executes the Boot ROM program, which verifies the user program in Flash and then jumps to execute the user program.

　　In J-link commander, after selecting SWD to connect to the development board in the connet command, check the VTOR register of Cortex-M3, the value is 0x100000, that is, the interrupt vector table is at the starting address of Flash.

Cortex-M3 identified.
J-Link>halt
PC = 00101428, CycleCnt = 00000000
R0 = 00000000, R1 = 20005FCF, R2 = 02B1E211, R3 = 40000300
R4 = 00000000, R5 = 00000000, R6 = 0010017C, R7 = 20005FE8
R8 = 4200A700, R9 = 00081A00, R10= 3B0EAFAB, R11= 9DB74B1E
R12= 00000000
SP(R13)= 20005FE8, MSP= 20005FE8, PSP= 1D36F2F0, R14(LR) = 00101427
XPSR = 81000000: APSR = Nzcvq, EPSR = 01000000, IPSR = 000 (NoException)
CFBP = 00000000, CONTROL = 00, FAULTMASK = 00, BASEPRI = 00, PRIMASK = 00
J-Link>mem32 e000ed08 1
E000ED08 = 00100000
J-Link>mem32 100000 4
00100000 = 20006000 00100165 00120CCB 00120CCD

Therefore, the difference between the Cortex-m3 program image file format of RSL10 and STM32 can be seen as the difference in the Flash starting address.

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After the RSL10 is powered on and reset, the Boot ROM program is executed. The ROM program verifies the user program in the Flash and then jumps to execute the user program. The manual says