MSP430 MCU interrupt

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MSP430 MCU interrupt [Copy link]

Interrupts are a major feature of the MSP430 microprocessor. Effective use of interrupts can simplify programs and improve execution efficiency. Almost every peripheral module of the MSP430 can generate interrupts, laying the foundation for MSP430 programming for events (i.e., interrupts generated by peripheral modules). The MSP430 enters low-power mode when no event occurs. When an event occurs, the CPU is awakened by an interrupt. After the event is processed, the CPU enters a low-power state again. Since the CPU's operating speed and exit from low power consumption are very fast, in applications, the CPU is in a low-power state most of the time.

There are three types of MSP430 interrupts: system reset, non-maskable interrupt, and maskable interrupt.

(1) The interrupt vector for system reset is 0xFFFE.

(2) The interrupt vector of a non-maskable interrupt is 0xFFFC. When responding to a non-maskable interrupt, the hardware automatically resets OFIE, NMIE, and ACCVIE. The software first determines the interrupt source and resets the interrupt flag, and then executes the user code. Before exiting the interrupt, OFIE, NMIE, and ACCVIE need to be set so that the interrupt can be responded to again. Special attention should be paid: After setting OFIE, NMIE, and ACCVIE, the interrupt corresponding program must be exited immediately, otherwise the interrupt will be triggered again, resulting in interrupt nesting, which will cause stack overflow and make the program execution result unpredictable.

(3) Maskable interrupts are interrupts from peripheral modules with interrupt capabilities, including interrupts generated by overflows when the watchdog timer is operating in timer mode. Each interrupt can be masked by its own interrupt control bit or by the global interrupt control bit.

When multiple interrupt requests occur, the highest priority interrupt is responded to. When responding to an interrupt, MSP430 will reset the non-maskable interrupt control bit SR.GIE. Therefore, once an interrupt is responded to, even if a higher priority maskable interrupt occurs, the interrupt currently being responded to will not be interrupted to respond to another interrupt. However, the SR.GIE reset does not affect non-maskable interrupts, so interrupt requests of non-maskable interrupts can still be accepted.

The process of interrupt response: (1) If the CPU is in active state, complete the current instruction; (2) If the CPU is in low power state, exit the low power state; (3) Push the PC value of the next instruction into the stack; (4) Push the status register SR into the stack; (5) If there are multiple interrupt requests, respond to the highest priority interrupt; (6) The interrupt request flag of a single interrupt source is automatically reset, and the flag of multiple interrupt sources remains unchanged, waiting for software reset; (7) The general interrupt enable bit SR.GIE is reset. The CPUOFF, OSCOFF, SCG1, V, N, Z, and C bits in the SR status register are reset; (8) The corresponding interrupt vector value is loaded into the PC register, and the program starts executing from this address.

The process of interrupt return: (1) Restore the PC value from the stack. If the CPU is in low-power mode before responding to the interrupt, the interrupt can be masked and the low-power mode can still be restored; (2) Restore the PC value from the stack. If the CPU is not in low-power mode before responding to the interrupt, the program continues to execute from this address.