MSP430F5438 clock system

火辣西米秀

MSP430F5438 clock system [Copy link]

MSP430F5438 clock system To understand a chip, the most intuitive thing is the official chip features (FEATURES); to use a chip well, you must understand the various functions of the chip from the data sheet; to develop a chip, we must start from the most basic clock system. This article focuses on the clock system of MSP430F5438, which is also the clock system of the entire 5 series. This is the first 430 chip I have come into contact with. If there are any errors, please correct me.

The Unified Clock System (UCS) provides different clocks for the chip. As shown in the figure below, the 5438 has four clock systems, namely the auxiliary clock (ACLK), the main clock (MCLK), the subsystem clock (SMCLK), and the dedicated clock (MODCLK). First, let's look at the sources of these clocks.

In addition to the dedicated clock, they can all come from XT1CLK, VLOCLK, REFOCLK, DCOCLK, DCOCLKDIV, XT2CLK, and you only need to configure the corresponding registers to select as needed. Among them, XT1CLK comes from the external XIN and XOUT pins through the OSC register, usually using a 32768Hz crystal oscillator; VLO (Very-Low-Power Low-Frequency Oscillator) and REFO (Low-Frequency Reference Oscillator) are directly generated by the OSC register (internal clock); DCOCLK (Digitally-Controlled Oscillator) and DCOCLKDIV (obtained by DCO division) come from the FLL (FrequencyLocked Loop) register (internal digital clock); XT2CLK comes from the external XT2IN and XT2OUT pins.

After the 5438 chip PUC (Power up clear), the default configuration of UCS (Unified Clock System) is: 1.

XT1 works in LF (Low-Frequency) mode as ACLK (conflicts with item 5, but that’s what the manual says, and I don’t understand it); 2.

DCOCLKDIV is used as MCLK; 3.

DCOCLKDIV is used as SMCLK; 4.

FLL works, and XT1CLK is used as the reference clock of FLL (FLLREFCLK); 5.

If XTIN and XTOUT are not configured, they will be used as general I/O ports, and XT1 will be disabled; they will be used as XT1 only after configuration; 6.

XT2IN and XT2OUT are used as general I/O ports, and XT2 is disabled.

Now let's start configuring the clocks. I will explain the configuration of one of the clocks, MCLK (master clock), and the other clocks are similar.

To get MCLK, you need to configure the registers (adjustment module) shown above. The registers that need to be configured are DIVM (division selection), SELM (clock source selection), CPUOFF (turn off the CPU, because it is the main clock, so turning off MLCK is equivalent to turning off the CPU), MCLK_REQEN (MCLK conditional requests conditional request enable), MCLK_REQ (no configuration is required, from the manual, the function is: if the peripheral module needs its correct operation, it needs it to automatically adjust from the UCS module, regardless of the current operation mode).

Next, let’s talk about the internal clock sources VLO and REFO as well as DCO and MODOSC.

REFO is a built-in reference clock, which is very stable and is generally used as the clock reference of FLL. The REFOCLK on MSP430F5438 is 32768Hz.

MODOSC is a dedicated clock (I know it can be used for AD sampling), about 5MHz (I don't know why there is no information about it in the manual). VLO is a built-in low-frequency clock. On 5438, its frequency is 6-14kHz. DCO is Digitally-Controlled Oscillator. It can generate a very high-frequency and relatively stable clock through FLL. By configuring FLL, it can even generate clock signals of more than 100MHz. FLL is Frequency Locked Loop. It can stabilize the output of DCO through feedback. The following figure is its block diagram: First, it needs a reference, which can be one of XT1, XT2, and REFO. After FLL is enabled (enabled by default), the DCO and MOD in the figure do not need to be set, and FLL will adjust these two values automatically. The frequency of DCO output is related to the following quantities: FLLD, FLLN, FLLREFDIV, FLLREFCLK. The calculation formula is as follows: fDCOCLK= D × (N + 1) × (fFLLREFCLK ÷ n) fDCOCLKDIV= (N + 1) × (fFLLREFCLK ÷ n) Where D=1, 2, 4, 8, 16, 32 (corresponding to FLLD=0, 1, 2, 3, 4, 5) N=FLLN n=1, 2, 4, 8, 12, 16 (corresponding to FLLREFDIV=0, 1, 2, 3, 4, 5) fFLLREFCLK is the actual frequency of REFO, XT1 or XT2.

That's about it for the clock system. It looks complicated but it's actually quite simple. You can only understand what you don't fully understand by trying it on the board yourself. Here is my own 5438 clock configuration. #include "msp430.h" int main( void ){

// Stop watchdog timer to prevent time out reset

WDTCTL = WDTPW + WDTHOLD;

P11DIR = BIT2 + BIT1 + BIT0;

// P11.2,1,0 to output direction

P11SEL = BIT2 + BIT1 + BIT0;

// P11.2 to output SMCLK, P11.1

// to output MCLK and P11.0 to

// output ACLK

//ACLK = REFO = 32kHz, MCLK = SMCLK = 25MHz

UCSCTL3 |= SELREF__REFOCLK;

// Set DCO FLL reference = REFO

UCSCTL4 |= SELA__REFOCLK;

// Set ACLK = REFO

__bis_SR_register(SCG0);

// Disable the FLL control loop

UCSCTL0 = 0x0000;

// Set lowest possible DCOx, MODx

UCSCTL1 = DCORSEL_7;

// Select DCO range 25MHz operation

UCSCTL2 = FLLD_1 +762;

// Set DCO Multiplier for 25MHz

// (N + 1) * FLLRef = Fdco

// (762 + 1) * 32768 = 25MHz

// Set FLL Div = fDCOCLK/2

__bic_SR_register(SCG0);

// Enable the FLL control loop

// Worst-case settling time for the DCO when the DCO range bits have been

// changed is nx 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx

// UG for optimization.

// 32 x 32 x 25 MHz / 32,768 Hz = 782000 = MCLK cycles for DCO to settle

__delay_cycles(782000);

// Loop until XT1,XT2 & DCO fault flag is cleared

do

{

UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);

// Clear XT2,XT1,DCO fault flags

SFRIFG1 &= ~OFIFG;

// Clear fault flags

}while (SFRIFG1&OFIFG);

// Test oscillator fault flag

while(1);

// Loop in place

return 0;}