【AT32F435 Review】 Clock Tree Understanding and Clock Configuration
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【Ateli AT-START-F435】Clock tree understanding and configuration
This article mainly studies the clock tree function of AT32F435. The reference code is AT32F435_437_Firmware_Library_V2.1.2\project\at_start_f435\templates
The code initialization part in the template initializes the clock. This section is briefly introduced.
system_clock_config();
Clock Tree
Below is the clock tree of AT32F435. The clock sources are HEXT oscillator clock (external clock 4-25MHz) and HICK oscillator clock (internal clock 48MHz). After selection, they pass through the pre-divider, multiplier VCO, and post-divider to output the PLL clock SCLK (maximum 288MHz) as the clock of the AHB bus.
The system clock HCLK provides the clock signal to the systick timer after being divided by 8. It can also be directly used as the CPU clock FCLK and provide the clock to the ADC after being divided by 2, 3, 4, 5...17 ( maximum 80 MHz ) .
The timer uses APB1/2 as the clock . In particular, when the APB pre-scaling factor is 1, the timer clock frequency is equal to the APB1/2 clock frequency; when the APB pre-scaling factor is not 1, the timer clock frequency is equal to twice the APB1/2 clock frequency. ( This is similar to STM 32 )
The USB clock can be switched between HICK and PLL divided clock.
Clock Configuration
First, use the following function to reset the crm clock configuration;
/* reset crm */
crm_reset();
Enable chip power control clock
/* enable pwc periph clock */
crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE);
AT32F435/437 series devices have three power domains - VDD/VDDA domain, 1.2V domain and battery power domain. The VDD/VDDA domain is powered directly by the power supply, the 1.2V domain is powered by the LDO embedded in the VDD/VDDA domain, and the battery power domain is powered by the VBAT pin. The sleep mode, deep sleep mode and standby mode can be realized by configuring the chip's voltage management PWC to achieve a balance between CPU running time, speed and power consumption. Use the following function to configure the chip's internal LDO voltage.
In this process, the main frequency f HCLK is configured to 288MHz, so the LDO voltage needs to be configured to 288MHz.
/* config ldo voltage */
pwc_ldo_output_voltage_set(PWC_LDO_OUTPUT_1V3);
Set the Flash clock. The Flash clock limit is 104MHz, so 288MHz is divided by 3 to 96MHz.
/* set the flash clock divider */
flash_clock_divider_set(FLASH_CLOCK_DIV_3);
Set the clock source to an external crystal
crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
/* wait till hext is ready */
while(crm_hext_stable_wait() == ERROR)
{
}
Configure the PLL parameters so that HCLK=288Mhz. The parameter setting method is as follows:
crm_pll_config(CRM_PLL_SOURCE_HEXT, 144, 1, CRM_PLL_FR_4);
/* enable pll */
crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL, TRUE);
/* wait till pll is ready */
while(crm_flag_get(CRM_PLL_STABLE_FLAG) != SET)
{
}
Of course, you can also use the official configuration tool to set it up, which can directly generate the code for several configuration files. It is similar to CubeMx, but currently only for clocks, and there is no peripheral graphical configuration tool.
Configure AHB bus 288MHz, APB2 144MHz, APB1 144MHz
/* config ahbclk */
crm_ahb_div_set(CRM_AHB_DIV_1);
/* config apb2clk, the maximum frequency of APB1/APB2 clock is 144 MHz */
crm_apb2_div_set(CRM_APB2_DIV_2);
/* config apb1clk, the maximum frequency of APB1/APB2 clock is 144 MHz */
crm_apb1_div_set(CRM_APB1_DIV_2);
Enable automatic frequency switching. The manual description is as follows:
/* enable auto step mode */
crm_auto_step_mode_enable(TRUE);
Set the PLL clock to the system clock
/* select pll as system clock source */
crm_sysclk_switch(CRM_SCLK_PLL);
/* wait till pll is used as system clock source */
while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL)
{
}
Disable automatic switching and update system clock
/* disable auto step mode */
crm_auto_step_mode_enable(FALSE);
/* update system_core_clock global variable */
system_core_clock_update();
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