MSP430F5438 study notes initialization XT1

火辣西米秀

MSP430F5438 study notes initialization XT1 [Copy link]

// Clock default
// FLL clock FLL selects XT1
// Auxiliary clock ACLK selects XT1 32768Hz
// Main system clock MCLK selects DCOCLKDIV 1048576Hz
// Subsystem clock SMCLK selects DCOCLKDIV 1048576Hz
#include <msp430.h>
int main(void)
{
WDTCTL = WDTPW+WDTHOLD; // Stop watchdog
P4DIR |= BIT0; // P4.0 output status

// Start XT1
P7SEL |= 0x03; // P7.0 P7.1 peripheral function
UCSCTL6 &= ~(XT1OFF); // XT1 turn on
UCSCTL6 |= XCAP_3; // internal capacitor
do
{
UCSCTL7 &= ~XT1LFOFFG; // clear XT1 error flag
}while (UCSCTL7&XT1LFOFFG); // check XT1 error flag

while(1)
{
P4OUT ^= BIT0; // flip P4.0
__delay_cycles(60000); // software delay
}
}