Playing with Zynq Serial 2——GPIO peripherals of Zynq PS

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Playing with Zynq Serial 2——GPIO peripherals of Zynq PS [Copy link]

Overview

The Zynq GPIO peripheral controls up to 54 MIO pins and can also be connected to the PL through the EMIO interface (supporting up to 64 input pins or 128 output pins). The GPIO peripheral can be divided into 4 banks .

The main features of the GPIO peripheral are as follows:

● 54 GPIO signals are brought out through MIO pins.

● 192 GPIO signals are connected to PL pins through the EMIO interface (64 input pins; 128 output pins, including 64 actual output pins and 64 output enable pins).

● Each GPIO can be independently programmed as input, output or interrupt interface.

● Enable signal, data write operation in bit or bank units, and direction control signal.

● Each GPIO has programmable interrupt control

The functional block diagram of GPIO is shown below.

The GPIO peripherals are divided into 4 banks .

● Bank0 consists of 32-bit MIO pins pin[31:0].

● Bank1 consists of 22-bit MIO pins pin[53:32].

● Bank2 consists of the 32-bit EMIO signal EMIO[31:0].

● Bank3 consists of the 32-bit EMIO signal EMIO[63:32].

2 GPIO internal structure

The internal structure of GPIO is shown in the figure.

GPIO can be configured as input or output signal. DATA_RO register can feedback the current GPIO input ( OE signal is low) or output ( OE signal is high) state value. By setting the MASK_DATA register, one or more specific GPIOs in a bank can be controlled.

The functions of several other main registers are as follows.

● DATA register. When GPIO is configured as output, this register is used to configure the output level value of GPIO. This register writes the output value of all 32 GPIOs at one time; when reading this register, the returned value is the written level state, not necessarily the actual level state.

● MASK_DATA_LSW register: This register is used to mask the lower 16 bits of the DATA register that do not need to be updated.

● MASK_DATA_MSW register: This register is used to mask the upper 16 bits of the DATA register that do not need to be updated.

● DIRM register. Direction control register. This register is used to control the input and output direction of GPIO. A high level indicates output, and a low level indicates input.

● OEN register. Output enable. When GPIO is configured as an output pin, this register is valid. A high level indicates output enable, and a low level indicates output disable.


This content was originally created by EEWORLD forum user ove. If you want to reprint or use it for commercial purposes, you must obtain the author's consent and indicate the source

hotsauce1861

I took a look today. Zynq is an ARM dual-core with FPGA as a peripheral. This piece of film will cost a lot of US dollars.