Playing with Zynq Serial 35——Online board debugging based on Vivado Virtual IO

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Playing with Zynq Serial 35——Online board debugging based on Vivado Virtual IO [Copy link]

1 Overview

For an introduction to board-level debugging based on Vivado , please refer to the document "Playing with Zynq- Basics: Overview of Online Board-Level Debugging Based on Vivado.pdf ". Here we take the zstar_ex55 project as an example to introduce and practice the use of FPGA Virtual IO (VIO for short ) .

2 Detection phase

Identify the signals to be detected by VIO as shown in the figure. For VIO , reg_rdtest is the signal we want to write to the axi_gp_data.v module; reg_second is the data we read from the axi_gp_data.v module. In other words, if we want to use VIO to detect these signals, reg_rdtest is the signal we want to generate from VIO ( VIO output ); reg_second is the signal we display on VIO ( VIO input ).

Figure 1. Identify the detection signal

As shown in the figure, in the IP Catalog , click Debug & Verification --> Debug --> VIO (Virtual Input/Output) to open the VIO IP core configuration page.

Figure VIO IP core

As shown in the figure, in the VIO configuration page, set the number of Input Probe Count in General Options , that is, the number of signals output from the FPGA to the VIO for observation and display (the bit width of each signal can be set in PROBE_IN Ports ); at the same time, set the number of Output Probe Count , that is, the number of signals that need to be sent to the FPGA for real-time changes (the bit width of each signal can be set in PROBE_OUT Ports ). The reg_second signal is an input probe , so set the Input Probe Count to 1 ; the four reg_rdtest signals are output probes , so set the Output Probe Count to 1 .

Figure 1. General Options page of VIO configuration

As shown in the figure, the bit width of each input signal can be set in PROBE_IN Ports . The bit width of the reg_second input port is 32 , so the bit width of PROBE_IN0 is set to 32 .

Figure 1. PROBE_IN Ports page of VIO configuration

As shown in the figure, the bit width of each output signal can be set in PROBE_OUT Ports . The bit width of reg_rdtest is 32 , so the bit width of PROBE_OUT0 is set to 32 .

Figure 1. PROBE_OUT Ports page of VIO configuration

As shown in the figure, under Source --> IP Sources , you can see the vio_0 IP . After expanding the Instantiation Template , you can see two versions of instantiation templates: VHDL and Verilog .

Figure VIO instantiation template file

The code of the instantiation template file is shown in the figure. Copy the code of the instantiation template, modify the signal names in the corresponding brackets and match them with those in the FPGA system, and the VIO code integration is completed .

Illustration template file code

As shown in the figure, in the module axi_gp_data.v , the VIO module is instantiated as follows.

Illustration of VIO IP core module

3. Implementation Phase

After completing the basic configuration of VIO and instantiation of the IP core, fully compile the project and generate a bit file.

4Analysis Phase

As shown in the figure, the .bit file generated by the project compilation is downloaded to the FPGA , and the .elf file generated by the embedded software is run on the processor.

As shown in the figure, under Hardware Manager --> Hardware , double-click to open hw_vio_1 , which is the debugging interface of the instantiated VIO .

Figure Hardware window

In the New Dashboard dialog box that pops up , as shown in the figure, check hw_vio_1 and click OK .

Figure New Dashboard dialog box

As shown in the figure, in the dashboard_2 interface, click the "+" sign on the left , the Add Probes pops up , select all signals, and click OK . All VIO connected signals are added to the dashboard_2 debugging interface.

Figure 2. Add available VIO interface signals

As shown in the figure, click to select the row where the signal name is located, right-click, and click Radix in the pop-up menu to see all supported Value display bases. You can click Unsigned Decimal , which is unsigned decimal.

At this time, the reg_second register displays data in decimal format that increases by 1 every second.

In the connected PuTTY print window, a line of data will be printed every 5 seconds or so, which is the value of the reg_rdtest register.

In the VIO debug window, we also noticed that the reg_rdtest register displays hexadecimal [H]0000_0000 by default . You can move the mouse over this value and click to modify the data to [H]5511_6699 .

Then we can see that the VIO input Data printed on PuTTY is also updated.

This content is originally created by EEWORLD forum user ove . If you want to reprint or use it for commercial purposes, you must obtain the author's consent and indicate the source