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Playing with Zynq Serial 17 - Creating a New Vivado Project [Copy link]

1Create a new Vivado project

In this section, we will create an FPGA project using Vivado .

First, we create a folder named "project" on the computer's hard disk . Note that the path name of this folder should not contain any Chinese characters or symbols (except underscores), that is, it should be mainly numbers and letters. For example, my path is "D:\myfpga\Zstar\project" .

Open Vivado and enter the main interface. As shown in the figure, we click the "Create New Project" icon to create a new project.

As shown in the figure, a prompt interface appears, click the "Next" button to continue.

As shown in the figure, enter the project name ( Project name ) and the project storage path ( Project location ). The Create project subdirectory option is used to select whether to create a folder with the same name as the project name in the already set project storage path to store the current project (this example does not check it, which means that the final project storage path is E:/myfpga/Zstar/project/zstar_ex01 ).

As shown in the figure, check RTL Project and click Next to continue.

As shown in the figure, in the Add Sources page, if there are already written Verilog or VHDL code source files, you can click + to add them; if not, just click Next to proceed to the next step.

As shown in the figure, the Add Existing IP page is the same. If there is no designed IP file to be added, continue to Next to proceed to the next step.

As shown in the figure, if there is a constraint file, you can add it. If not, continue to Next to proceed to the next step.

As shown in the figure, select xc7z010clg400-3 as the FPGA device model of the current project.

Finally, the New Project Summary interface as shown in the figure will pop up , listing all the project information set previously for easy verification. We click Finish to complete the project creation.

2 Overview of the Vivado Project Interface

At this point, as shown in the figure, the main interface of Vivado 's project appears before us.

And as shown in the figure, some project files are automatically generated in the folder "project/zstar_ex01" .

Congratulations, the Vivado project has been created.



This content is originally created by EEWORLD forum user ove . If you want to reprint or use it for commercial purposes, you must obtain the author's consent and indicate the source

This post is from FPGA/CPLD
 

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