Can't the same vivado project have multiple simulation files?
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A new vivado project file was created. At the beginning, it only had uv_calculation and simulation file vtf_uv_calculation.
After simulation, there is no problem with the waveform.
Later, scaler_3to2 and simulation file vtf_scaler_3to2 were added and set as the top-level files. The simulation results are all "Z" and "X". The hierarchical relationship after adding the files is as follows:
The simulation results after adding the scaler file (both calculation and scaler simulation outputs are "Z" and "X"):
Calculation simulation (the output waveform also has u_d and u_v, but the simulation stimulus file does not define these two variables):
Scaler file simulation waveform:
The calculation file was simulated without any problems before, but it became a problem after adding the scaler.
Now there is no problem in copying the calculation separately and creating a new project for testing:
Finally, attach the calculation and scaler code:
uv_calculation：
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2022/06/23 09:39:54
// Design Name:
// Module Name: uv_calculation
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module uv_calculation(
input clk,
input rst_n,
input col_cnt,
input row_cnt,
output [9:0] u,
output [9:0] v
);
reg [10:0] u_d;
reg [10:0] v_d;
always@(posedge clk or negedge rst_n) begin
if(rst_n == 1'b0) begin
u_d <= 10'd0;
v_d <= 10'd0;
end
else begin
u_d <= col_cnt * 10'd1023 * 3 / 2 - col_cnt * 10'd1023;
v_d <= row_cnt * 10'd1023 * 3 / 2 - row_cnt * 10'd1023;
end
end
assign u = u_d;
assign v = v_d;
endmodule
vtf_uv_calfulation:
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2022/06/23 09:40:57
// Design Name:
// Module Name: vtf_uv_calculation
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module vtf_uv_calculation(
);
reg clk;
reg rst_n;
reg col_cnt;
reg row_cnt;
wire [9:0] u;
wire [9:0] v;
uv_calculation uut
(
.clk(clk),
.rst_n(rst_n),
.col_cnt(col_cnt),
.row_cnt(row_cnt),
.u(u),
.v(v)
);
initial begin
clk = 0;
rst_n = 0;
col_cnt = 0;
row_cnt = 0;
#50;
clk = 1;
rst_n = 1;
end
always #5 clk = ~clk;
always@(posedge clk) begin
col_cnt = {$random}%2;
row_cnt = {$random}%2;
end
endmodule
scaler_3to2:
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2022/06/22 17:05:46
// Design Name:
// Module Name: scaler_3to2
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module scaler_3to2(
input clk,
input rst_n,
input [ 9: 0] u,
input [ 9: 0] v,
input [23: 0] ref_data00,
input [23: 0] ref_data01,
input [23: 0] ref_data10,
input [23: 0] ref_data11,
output pix_valid,
output [23: 0] pix_out
);
reg [23: 0] pix_out_d;
reg pix_valid_d;
reg [ 7: 0] ref_red;
reg [ 7: 0] ref_green;
reg [ 7: 0] ref_blue;
assign pix_out = pix_out_d;
assign pix_valid = pix_valid_d;
always@(posedge clk or negedge rst_n) begin
if(rst_n == 1'b0) begin
pix_out_d <= 24'd0;
pix_valid_d <= 1'b0;
end
else begin
pix_out_d <= (11'd1023 - u) * (11'd1023 - v) * ref_data00 + (11'd1023 - v) * u * ref_data10
+ (11'd1023-u) * v * ref_data01 + u * v * ref_data11;
pix_valid_d <= 1'b1;
end
end
endmodule
vtf_scaler_3to2:
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2022/06/22 17:20:15
// Design Name:
// Module Name: vtf_scaler_3to2
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module vtf_scaler_3to2();
reg clk;
reg rst_n;
reg [ 9: 0] u;
reg [ 9: 0] v;
reg [23: 0] ref_data00;
reg [23: 0] ref_data01;
reg [23: 0] ref_data10;
reg [23: 0] ref_data11;
wire pix_valid;
wire [23: 0] pix_out;
scaler_3to2 uut
(
.clk(clk),
.rst_n(rst_n),
.u(u),
.v(v),
.ref_data00(ref_data00),
.ref_data01(ref_data01),
.ref_data10(ref_data10),
.ref_data11(ref_data11),
.pix_valid(pix_valid),
.pix_out(pix_out)
);
initial begin
clk = 0;
rst_n = 0;
u = 10'd0;
v = 10'd0;
ref_data00 = 24'd0;
ref_data01 = 24'd0;
ref_data10 = 24'd0;
ref_data11 = 24'd0;
#50;
clk = 1;
rst_n = 1;
end
always #5 clk = ~clk;
always@(posedge clk) begin
u = {$random}%2;
v = {$random}%2;
ref_data00 = {$random};
ref_data01 = {$random};
ref_data10 = {$random};
ref_data11 = {$random};
end
endmodule
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