Design of Serial Universal Asynchronous Receiver/Transmitter Based on FPGA

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Design of Serial Universal Asynchronous Receiver/Transmitter Based on FPGA [Copy link]

UART (Universal Asynchronous Receiver Transmitter) is a widely used short-distance serial transmission interface. It is often used in short-distance, low-speed, and low-cost communications. Chips such as 8250, 8251, and NS16450 are all common UART devices. Basic UART communication only requires two signal lines (RXD and TXD) to complete data communication, and reception and transmission are full-duplex. TXD is the UART transmitter, which is the output; RXD is the UART receiver, which is the input.
　　The basic characteristics of UART are: (1) There are two states on the signal line, which can be distinguished by logic 1 (high level) and logic 0 (low level). When the transmitter is idle, the data line should remain in the logic high state. (2) Start Bit: The transmitter starts a character transmission by sending a start bit. The start bit puts the data line in the logic 0 state, prompting the receiver that data transmission is about to begin.
　

　　(3) Data Bits: After the start bit comes the data bit. The data bit is usually 8 bits per byte (6 or 7 bits are also possible), with the LSB in front and the MSB in the back. (4) Parity Bit: It can be considered a special data bit. The parity bit is usually used to determine whether the received data bit has errors, usually parity check. In use, this bit is often canceled. (5) Stop Bit: The
　　stop bit is at the end, used to mark the end of a character transmission, and it corresponds to the logic 1 state. (6) Bit Time: The time width of each bit. The bit widths of the start bit, data bit, and parity bit are the same. The stop bit has 0.5 bit, 1 bit, or 1.5 bit formats, usually 1 bit. (7) Frame: The time interval from the start bit to the stop bit is called a frame. (8
　　) Baud Rate: The transmission rate of UART, used to indicate the speed of data transmission. In serial communication, data is transmitted bit by bit, so the transmission rate is expressed by the number of data bits transmitted per second, which is called the baud rate. For example, the baud rate 9600 = 9600bps (bits/second).
　　FPGA UART system composition: As shown in the figure below, FPGA UART consists of three sub-modules: baud rate generator; receiving module; sending module;
　　

　　Module design: The system consists of four parts: top module; baud rate generator; UART receiver; UART transmitter.
　　The top module of the asynchronous receiver and transmitter consists of a baud rate generator, a UART receiver and a UART transmitter. The purpose of the UART transmitter is to convert the parallel data to be output into a TXD signal serial output according to the basic UART frame format. The UART receiver receives the RXD serial signal and converts it into parallel data.
　　The baud rate generator is specifically used to generate a local clock signal that is much higher than the baud rate to continuously sample the input RXD so that the receiver and the transmitter are synchronized. The baud rate generator is actually a frequency divider. The baud rate division factor can be calculated based on the given system clock frequency (crystal oscillator clock) and the required baud rate, and the calculated baud rate division factor is used as the division number of the frequency divider. The baud rate division factor can be changed according to different application needs.
　　Since the serial data frame and the receiving clock are asynchronous, the transition from logic 1 to logic 0 can be regarded as the start bit of a data frame. However, in order to avoid the influence of glitches and obtain the correct start bit signal, it is required that at least half of the received start bits are logic 0 during the baud rate clock sampling process to determine that the received start bit is a start bit. Since the internal sampling clock bclk cycle (generated by the baud rate generator) is 16 times the frequency of the sending or receiving baud rate clock, the start bit needs to be received with logic 0 of at least 8 consecutive bclk cycles before it is considered to be received. Then the data bit and parity bit will be sampled once every 16 bclk cycles (that is, each baud rate clock is sampled once). If the start bit is indeed 16 bclk cycles long, then the following data will be sampled at the midpoint of each bit.