Design based on FPGA configuration circuit

FPGA configuration methods are flexible and diverse. According to whether the chip can actively load configuration data by itself, it is divided into master mode, slave mode and JTAG mode. The typical master mode loads the configuration bit stream in the off-chip non-volatile (data is not lost when power is turned off) memory. The clock signal (called CCLK) required for configuration is generated internally by the FPGA, and the FPGA controls the entire configuration process. The slave mode requires an external master intelligent terminal (such as a processor, microcontroller or DSP, etc.) to download data into the FPGA. Its biggest advantage is that the FPGA configuration data can be placed in any storage location of the system, including: Flash, hard disk , networking, and even in the code running on the rest of the processors. JTAG mode is the debugging mode, which can download the bit file stream in the PC to the FPGA and will be lost when the power is turned off. In addition, Xilinx currently has Internet-based, mature reconfigurable logic technology System ACE solution.

(1) Main mode

In the main mode, after the FPGA is powered on, it automatically reads the configuration data from the corresponding external memory into the SRAM to realize internal structure mapping; the main mode can be divided into serial mode (single bit stream) according to the bit width of the bit stream. ) and parallel mode (byte-width bitstream). Such as: main serial mode, main SPI Flash serial mode, internal main SPI Flash serial mode, main BPI parallel mode and main parallel mode, as shown in Figure 5-19.

(2) Slave mode

In slave mode, FPGA acts as a slave device, and the corresponding control circuit or microprocessor provides the timing required for configuration to realize the download of configuration data. The slave mode is also divided into two categories: serial mode and parallel mode according to the bit width of the bit stream. Specifically, it includes three categories: slave serial mode, JTAG mode and slave parallel mode. Its summary is shown in Figure 5-20.

(3)JTAG mode

In the JTAG mode, the clock for communication between the PC and the FPGA is the TCLK of the JTAG interface, and the data enters the FPGA directly from the TDI to complete the configuration of the corresponding functions.

Figure 5-19 Schematic diagram of common main mode download methods

Figure 5-20 Schematic diagram of commonly used slave mode download methods

Currently, mainstream FPGA chips support various commonly used master and slave configuration modes and JTAG to reduce the impact of configuration circuit mismatch on the overall system. In the master configuration mode, the FPGA generates its own clock and loads the configuration data from the external memory, whose bit width can be a single bit or byte; in the slave mode, the external processor uses a synchronous serial interface to load the configuration data in bits or words. The section width feeds the configuration data into the FPGA chip. In addition, multiple FPGAs can share the same external memory in the form of a JTAG daisy chain, and one/multiple FPGAs can also read configuration data and user-defined data from multiple external memories.

There are 5 common configuration modes of Xilinx FPGA: master serial mode, slave serial mode, Select MAP mode, Desktop configuration and direct SPI configuration. In the slave string configuration, the FPGA receives configuration bit data from an external PROM or other device, and completes the configuration under the action of the clock CCLK generated by the FPGA. Multiple FPGAs can form a daisy chain and obtain data from the same configuration source. The configuration data in Select MAP mode is parallel and is the fastest configuration mode. SPI configuration is mainly used in FLASH circuits with SPI interface. Taking the Spartan-3E series chip as an example, the configuration circuits of various modes are given below.

5.5.2 Main string mode - the most commonly used FPGA configuration mode

1. Configure single-chip FPGA

In the main string mode, the CCLK pin of the FPGA provides the working clock to the PROM, and the corresponding PROM sends data from the D0 pin to the DIN pin of the FPGA on the rising edge of CCLK. Regardless of the PROM chip type (even if it supports parallel configuration), only utilize its serial configuration capabilities. The single-chip main string configuration circuit of the Spartan3E series FPGA is shown in Figure 5-21. The main string mode is the simplest and most commonly used method among Xilinx's various configuration methods. Basically all programmable chips support the main string mode.

Figure 5-21 Spartan-3E main string mode configuration circuit

2. Key points in configuring the circuit

The three most critical points of the main string configuration circuit are the integrity of the JTAG chain, the setting of the power supply voltage, and the consideration of the CCLK signal. As long as there is a problem in any of these three steps, the PROM chip cannot be configured correctly.

(1)Integrity of the JTAG chain

FPGA and PROM chips have their own JTAG interface circuits. The so-called JTAG chain integrity refers to connecting the TMS and TCK of the JTAG connector, FPGA, and PROM together to ensure that the connection between the JTAG connector TDI and its TDO is formed. The closed loop of "TDI → (TDI~TDO) → (TDI~TDO) → JTAG connector TDO" of the JTAG connector, where (TDI~TDO) is a pair of input and output pins of the FPGA or PROM chip itself. The JTAG chain of the configuration circuit in Figure 5-12 goes from the TDI of the connector to the TDI of the FPGA, then from the TDO of the FPGA to the TDI of the PROM, and finally from the TDO of the PROM to the TDO of the connector, forming a complete JTAG chain, FPGA chip It is called the chain head chip. The positions of FPGA and PROM can also be exchanged as needed to make PROM the first chip in the chain.

(2) Power supply adaptability

As shown in Figure 5-22, since FPGA and PROM need to complete data communication, the interface levels of the two must be consistent, that is, the pin voltage Vcco_2 of the corresponding group of FPGA must be consistent with the input voltage of PROM Vcco, and the ideal value is 2.5 V, this is because the PROG_B and DONE pins of the FPGA are powered by Vccaux of 2.5V. Additionally, since the voltage to the JTAG connector is also provided by Vccaux of 2.5V, the VCCJ of the PROM must also be 2.5V. Therefore, if the interface voltage and the reference voltage are different, the pin voltage of the corresponding group needs to be set to be consistent with the reference voltage during the configuration stage; after the configuration is completed, switch it to the operating voltage required by the user. Of course, FPGA and PROM can also adapt to the 3.3V I/O level and JTAG level, but certain changes are required, that is, adding several external current-limiting resistors, as shown in Figure 5-22. In main string mode, the core voltage of XCFxxS series PROMs must be 3.3V, and the core voltage of XCFxxP series PROMs must be 1.8V.

Figure 5-22 Schematic diagram of 3.3V JTAG configuration circuit

Special attention should be paid to the two resistors RSER and RPAR in Figure 5-22. First, RSER = 68Ω limits the current flowing into each input to 9.5mA; secondly, N = 3 with the diodes of the three inputs conducting,

RPAR = VCCAUX min/NIIN = 2.375V/(3*9.5mA)

=83 Ω or 82 Ω (resistance with an error of less than 5% from the standard value)

(3) CCLK signal integrity

The CCLK signal is the clock signal for JTAG configuration data transmission, and its signal integrity is very critical. The FPGA configuration circuit initially operates at the lowest clock and will gradually increase the frequency unless otherwise specified. The CCLK signal is generated internally by the FPGA. For different chips and levels, its maximum value is shown in Table F-1.

Table 5-1 Maximum configuration clock frequency of different PROM chips

3. Configure multiple FPGAs

The configuration circuit of multi-chip FPGA is similar to that of single-chip, but multi-chip FPGA is divided into master and slave, and different configuration modes need to be selected. The typical configuration circuit of two Spartan 3E series FPGAs is shown in Figure 5-23. The two FPGAs have master and slave status.

Figure 5-23 Configuration circuit of two FPGAs in master-slave mode

Common problems with FPGA configuration failure

When configuring FPGA devices, configuration failures often occur. To sum up, the following situations are briefly summarized, and corresponding solutions are given.

1. JTAG chain scan failed

Solution: First, check whether the TCK and TMS pins of all chips are connected to the TCK and TMS of the JTAG interface; secondly, check whether the JTAG link of the configuration circuit is complete, from the TDI of the JTAG interface to the TDO and TDO of the chain head chip. ..., and then check whether the TDO of the chip at the end of the chain is connected to the TDO of the JTAG interface; finally, check whether the power supply is correct.

2. Unable to configure through computer parallel port

Solution: First, check whether the computer parallel port is plugged in properly; secondly, use a better quality parallel port configuration cable (Parallel Cable-IV) or a USB configuration cable with better signal quality to eliminate the problem of the download cable. For now, it's best to use a faster and more reliable USB download cable.

3. Unable to configure normally

Solution: Check whether there is interference signal or overshoot in the configuration clock signal CCLK or JTAG clock signal TCK. If there is interference, determine the source of the interference and add a filter circuit to eliminate the interference. If there is overshoot, it means that the impedance of the signal line may not match due to its long length, and a matching resistor needs to be added. Under normal circumstances, the lead length of the CCLK signal does not exceed 10cm. The clock signal quality can also be improved by adding a source-end matching resistor (33~100 Ω resistor).

In addition, if the bypass capacitor design of the FPGA chip is unreasonable or there are ground wires and bounce signals on the data lines, it will also cause configuration failure.

4. The DONE pin status is always low

Solution: Check whether the load on the DONE pin is too heavy and select an appropriate pull-up resistor.

5. The DONE pin has gone high, but the device still does not work properly.

Solution: First check whether the design is correct; secondly, if the design is correct, then check the startup sequence of the device, refer to the configuration process, and reset the startup sequence through the design tool.

6. Wrong mode pin selection

Solution: Select the configuration mode according to the mode selection pin M[2:0]. When the mode changes, you need to modify the configuration clock in the bit stream file to CCLK or TCK, otherwise the configuration may fail.

7. After the device is powered on, sometimes it can be configured successfully, sometimes it cannot.

Solution: In this case, data flow starts to occur when the reset is not completed during the period. The solution is to add a reset chip to extend the reset time.