A beginner was trapped by the garbage code of the development board for a whole night

lingking

A beginner was trapped by the garbage code of the development board for a whole night [Copy link]

I am using the AX309 development board from Heijin and I am a beginner in FPGA. Today I simulated the serial port routine in their tutorial. First, I had a problem simulating a simple clock divider module.

First, here is their code:

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Module Name:    clkdiv
// 产生一个波特率9600的16倍频的时钟，9600*16= 153600
// 相当于50MHz的326分频，50000000/153600=326
//////////////////////////////////////////////////////////////////////////////////
module clkdiv(clk50, clkout);
input clk50;              //系统时钟
output clkout;          //采样时钟输出
reg clkout;
reg [15:0] cnt;

//分频进程,对50Mhz的时钟326分频
always @(posedge clk50)   
begin
  if(cnt == 16'd162)
  begin
    clkout <= 1'b1;
    cnt <= cnt + 16'd1;
  end
  else if(cnt == 16'd325)
  begin
    clkout <= 1'b0;
    cnt <= 16'd0;
  end
  else
  begin
    cnt <= cnt + 16'd1;
  end
end
endmodule

The test code I wrote:

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module DIV_tb;

	// Inputs
	reg CLK_50M;
	// Outputs
	wire CLK_DIV;

	// Instantiate the Unit Under Test (UUT)
	clkdiv uut (
		.clk50(CLK_50M),
		.clkout(CLK_DIV)
	);

	initial begin
		// Initialize Inputs
		CLK_50M = 0;
	
		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
	end
	
		always
			begin
				#10	CLK_50M = ~CLK_50M;
			end 		  
	  
	  
endmodule

There seems to be no problem with the code, but when it is imported into modelsim for simulation, I am dumbfounded. The output of the module is always X, with a red line until the end of the simulation.

Then I read various books and compared the code, but I still couldn't figure out what went wrong. Later, I saw something related on a web page, and I suspected that the counter was not reset, which caused the state uncertainty. Then I changed the code, added the reset signal to the module and the testbench, and then the simulation results were correct, and the clock frequency division signal finally had output:

From this incident, we can see how important it is to write code rigorously and conduct simulation tests. This company's products are really misleading. However, objectively speaking, I still have to thank them. If it weren't for this, I wouldn't have realized the importance of reset and initial value.

lingking

This section is so cold. This section is so cold. This section is so cold. This section is so cold. This section is so cold. This section is so cold. This section is so cold.

郝旭帅

Many tutorials do not consider simulation, and just do it directly on the board.