JLink+GDBServer debugs the initialization code of S3C6410 bare board For OK6410 development board

There are two initialization methods for debugging bare boards. One is to use the burned uboot for initialization, and the other is to use JLink+GDBServer for initialization. The code refers to the information on the Internet and is modified according to the OK6410 development board at hand. The overall code is as follows:

# Connect to the J-Link GDBServer

target remote localhost:2331

# Set JTAG speed to 30 kHz

monitor endian little

monitor speed 30

# Reset the target

monitor reset

monitor sleep 10

#

# CPU core initialization

#

# Set the processor to service mode

monitor reg cpsr = 0xd3

# Config MMU

# Flush v3/v4 cache

monitor cp15 7, 7, 0, 0 = 0x0

monitor cp15 8, 7, 0, 0 = 0x0

# Disable MMU stuff and caches

monitor cp15 1, 0, 0, 0 =0x1002

# Peri port setup

monitor cp15 15, 2, 0, 4 = 0x70000013

# Disable watchdog

monitor MemU32 0x7e004000  =  0x00000000

monitor sleep 10

# Disable interrupt

monitor MemU32 0x71200014  =  0xffffffff

monitor MemU32 0x71300014  =  0xffffffff

monitor MemU32 0x7120000C  =  0x00000000

monitor MemU32 0x7130000C  =  0x00000000

monitor MemU32 0x71200F00  =  0x00000000

monitor MemU32 0x71300F00  =  0x00000000

# Set clock

monitor MemU32 0x7e00f900  =  0x000080de

monitor MemU32 0x7e00f000  =  0x0000ffff

monitor MemU32 0x7e00f004  =  0x0000ffff

monitor MemU32 0x7e00f008 = 0x0000ffff

monitor MemU32 0x7e00f028 = 0x00300000

monitor MemU32 0x7e00f020  =  0x01043310

monitor MemU32 0x7e00f00C  =  0x810a0301

monitor MemU32 0x7e00f010  =  0x810a0301

monitor MemU32 0x7e00f014 = 0x80200102

monitor MemU32 0x7e00f018 = 0x00000000

monitor MemU32 0x7e00f01c = 0x00000007

monitor sleep 1

# UART Init

monitor MemU32 0x7f008000 = 0x00220022

monitor memU32 0x7f008020 = 0x00002222

monitor memU32 0x7f005008 = 0x00000000

monitor memU32 0x7f00500c = 0x00000000

monitor memU32 0x7f005000 = 0x00000003

monitor memU32 0x7f005004 = 0x00000e45

monitor memU32 0x7f005028 = 0x00000033

monitor memU32 0x7f00502c = 0x0000dfdd

monitor memU32 0x7f005020 = 0x4f4f4f4f

monitor memU32 0x7f005020 = 0x4b4b4b4b

# Config Mobile DDR SDRAM

monitor MemU32 0x7e00f120  =  0x0000000d

monitor MemU32 0x7e001004  =  0x00000004

monitor MemU32 0x7e001010  =  0x0000040f

monitor MemU32 0x7e001014  =  0x00000006

monitor MemU32 0x7e001018  =  0x00000001

monitor MemU32 0x7e00101c  =  0x00000002

monitor MemU32 0x7e001020  =  0x00000006

monitor MemU32 0x7e001024  =  0x0000000a

monitor MemU32 0x7e001028  =  0x0000000c

monitor MemU32 0x7e00102c  =  0x0000010b

monitor MemU32 0x7e001030  =  0x0000000c

monitor MemU32 0x7e001034  =  0x00000002

monitor MemU32 0x7e001038  =  0x00000002

monitor MemU32 0x7e00103c  =  0x00000002

monitor MemU32 0x7e001040  =  0x00000002

monitor MemU32 0x7e001044  =  0x00000010

monitor MemU32 0x7e001048  =  0x00000010

monitor MemU32 0x7e00100C  =  0x0001001a

monitor MemU32 0x7e00104C  =  0x00000b45

monitor MemU32 0x7e001200  =  0x000150f0

monitor MemU32 0x7e001304  =  0x00000000

monitor MemU32 0x7e001008  =  0x000c0000

monitor MemU32 0x7e001008  =  0x00000000

monitor MemU32 0x7e001008  =  0x00040000

monitor MemU32 0x7e001008  =  0x00040000

monitor MemU32 0x7e001008  =  0x000a0000

monitor MemU32 0x7e001008  =  0x00080032

monitor MemU32 0x7e001004  =  0x00000000

# Setup GDB for faster downloads

#set remote memory-write-packet-size 1024

set remote memory-write-packet-size 4096

set remote memory-write-packet-size fixed

monitor speed 12000

break start_armboot

load

continue

Download line-by-line instructions:

Monitor reg cpsr = 0xd3

This line puts the CPU into management mode and sets the interrupt mask IFT M4 M3 M2 M1 M0, which corresponds to 0xB11010011 for 0xd3. I and F are set to set the interrupt and fast interrupt mask, and T is cleared, indicating that the current mode is ARM mode. M is set to 0xB10011, which is management mode.

monitor MemU32 0x7e004000 = 0x00000000

This line disables the watchdog, and the register description is as follows:

Watchdog timer [5]  0=Disable,  1=Enable

Clock select [4:3] 00:16  01:32  10:64  11:128

Interrupt generation [2] 0=Disable,  1=EnableReset enable/disable [0]

Monitor MemU32 0x71200014 = 0xFFFFFFFF

Monitor MemU32 0x71300014 = 0xFFFFFFFF

Set the VIC0INTENCLEAR and VIC1IntENCLEAR registers. Writing 0 to the register has no effect, and writing 1 will disable the corresponding interrupt:

Clears corresponding bits in the VICINTENABLE Register:0 = no effect1 = interrupt disabled in VICINTENABLE Register.There is one bit of the register for each interrupt source.

Other information on the Internet all writes 0 in it, which should be a mistake.

Monitor MemU32 0x7120000C = 0x00000000

Monitor MemU32 0x7130000C = 0x00000000

Set all interrupts to IRQ instead of FIQ. Write 0 to this register for IRQ and 1 for FIQ:

Selects type of interrupt for interrupt request:0 = IRQ interrupt (reset)1 = FIQ interruptThere is one bit of the register for each interrupt source

Monitor MemU32 0x71200F00 = 0x00000000

Monitor MemU32 0x71300F00 = 0x00000000

Set the VIC0ADDRERSS and VIC1ADDRESS registers to clear the currently pending interrupt:

Contains the address of the currently active ISR, with reset value0x00000000.A read of this register returns the address of the ISR and sets thecurrent interrupt as being serviced. A read must only be performedwhile there is an active interrupt.A write of any value to this register clears the current interrupt. Awrite must only be performed at the end of an interrupt serviceroutine.

Monitor MemU32 0x7e00f900 = 0x000080de

Set the OTHERS register to Synchronous mode. The online information does not set sync, so you need to test it.

Monitor MemU32 0x7e00f000 = 0x0000ffff

Monitor MemU32 0x7e00f004 = 0x0000ffff

Monitor MemU32 0x7e00f008 = 0x0000ffff

Set the APLL_LOCK, MPLL_LOCK and EPLL_LOCK registers to the maximum interval

Monitor MemU32 0x7e00f028 = 0x00300000

Set the CLK_DIV2 register, mainly to set UART_RATIO:

UART_RATIO     [19:16]

UART clock divider ratio

CLKUART = CLKUARTIN / (UART_RATIO + 1)

The setting here is CLKUART = CLKUARTIN / 4

Monitor MemU32 0x7e00f020 = 0x01043310

Set the CLK_DIV0 register to the following value:

PCLK_RATIO   [15:12]     0x3

HCLKX2_RATIO [11:9]      0x1

HCLK_RATIO   [8]         0x1

MPLL_RATIO   [4]         0x1

APLL_RATIO    [3:0]      0x0

According to the following calculation formula

PCLK = HCLKX2 / (PCLK_RATIO + 1)

HCLKX2 = HCLKX2IN / (HCLKX2_RATIO + 1)

HCLK = HCLKX2 / (HCLK_RATIO + 1)

DOUTMPLL = MOUTMPLL / (MPLL_RATIO + 1)

ARMCLK = DOUTAPLL / (ARM_RATIO + 1)

The calculation results obtained

PCLK = HCLKX2 / 4

HCLKX2 = HCLKX2IN / 2

HCLK = HCLKX2 / 2

DOUTMPLL = MOUTMPLL / 2

ARMCLK = DOUTAPLL

Monitor MemU32 0x7e00f00c = 0x810a0301

Monitor MemU32 0x7e00f010 = 0x810a0301

Set the APLL_CON and MPLL_CON registers,

The calculation formula is

FOUT = MDIV X END / (PDIV X 2SDIV)

For the APLL_CON register:

Enable   [31]         0x1

MDIV [25:16] 0x10a(266)

PDIV     [13:8]    0x3

SDIV     [2:0]     0x1

Then FOUT = 266 X 12 / (3 X 2) = 532

The same is true for the MPLL_CON register, which is also 532

Monitor MemU32 0x7e00f014 = 0x80200102

Monitor MemU32 0x7300f018 = 0x00000000

Setting the EPLL_CON0 register

Enable      [31]    0x1

MDIV       [23:16]   0x20

PDIV [13:8] 0x1

SDIV       [2:0]    0x2

Setting the EPLL_CON1 register

KDIV       [15:0]   0x0

According to the calculation formula: FOUT = (MDIV + KDIV / 216) X FIN / (PDIV X 2SDIV)

We can calculate FOUT = 32 X 12 / (1 X 4) = 96

Monitor MemU32 0x7e00f01c = 0x00000007

Setting the CLK_SRC register

UART_SEL   [13]   0x0    using MOUT epll

EPLL_SEL    [2]    0x1    using FOUT epll

MPLL_SEL [1] 0x1 using FOUT mpll

APLL_SEL    [0]     0x1   using FOUT apll

Monitor MemU32 0x7f008000 = 0x00220022

Setting the GPACON Register

GPA0         [3:0]     0x2   UART RXD[0]

GPA1         [7:4]     0x2   UART TXD[0]

GPA2         [11:8]    0x0   Input

GPA3         [15:12]   0x0   Input

GPA4         [19:16]   0x2   UART RXD[1]

GPA5         [23:20]   0x2   UART TXD[1]

Monitor MemU32 0x7f008020 = 0x00002222

Setting the GPBCON Register

GPB0     UART_RXD[2]

GPB1     UART TXD[2]

GPB2     UART RXD[3]

GPB3     UART TXD[3]

Monitor memU32 0x7f005008 = 0x00000000

Set the UFCON0 register:

FIFO disable

Monitor memU32 0x7f00500c = 0x00000000

Set up the UMCON0 register:

Modem interrupt Disable

Monitor MemU32 0x7f005000 = 0x00000003

Setting the ULCON0 register

Word Length 8-bit

One shop bit per frame

No parity Mode           Normal mode operation

Monitor MemU32 0x7f005004 = 0x00000e45

Setting UCON0 register

Clock selection EXT_UCLK1:  DIV_VAL=(EXT_UCLK1/(bps x16))-1

Tx Interrupt Type: Level

Rx Interrupt Type: Pulse

Rx Time Out  Enable: disable

Rx Error status interrupt enable: enable

Loop-back Mode: normal operation

Send break signal: normal transmit

Transmit Mode: Interrupt request or polling mode

Receive Mode: Interrupt request or polling mode

monitor memU32 0x7f005028 = 0x00000033

Div integer part is 0x33 (51)

Monitor memU32 0x7f00502c = 0x0000dfdd

Setting the UDIVSLOT0 register

0.83 * 16 = 13.3  = 13 so  0xdfdd