Understanding 28GHz 5G Communication Band RF Front-End Modules

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Understanding 28GHz 5G Communication Band RF Front-End Modules [Copy link]

With the expected imminent commercialization of 5G millimeter wave, the research and development of key companies in the industry is progressing smoothly, and the specification, design and verification of customized components have been completed. The basic component required to realize future millimeter wave 5G systems is the RF front-end module (FEM). This module includes the final amplifier stage of the transmitter and the front-end amplifier stage in the receiver and the transmit/receive switch (Tx/Rx) to support time division duplexing (TDD). The FEM must have high linearity in transmit mode and low noise figure in receive mode. Since millimeter wave 5G systems may require user terminals to use multiple FEMs to form a phased array architecture or a switch antenna beam architecture. Therefore, the FEM must be implemented in an efficient, compact and low-cost manner, and it is best to be simple to control and monitor.

　　This article describes the design, implementation, and verification of an RF front-end module MMIC (monolithic microwave integrated circuit) for the 28GHz 5G communication band (27.5 to 28.35GHz) that meets all of the above requirements. The RF front end was developed by Plextek RFI and implemented using WINSemiconductors' PE-15 4V, 0.15μm, enhanced GaAs PHEMT process. It is packaged in a compact, low-cost, SMT-compatible 5mm x 5mm secondary injection-compatible QFN package for high-volume, low-cost manufacturing. It covers 27 to 29GHz, thus supporting the full 28GHz 5G band.

　　1. Design goals

　　The design of the FEM transmit channel focuses on achieving high efficiency under power back-off to provide linear amplification, which is a requirement of 5G communication systems. The target power added efficiency (PAE) under power back-off is set at 6%, and the third-order intermodulation (IMD3) is less than -35dBc (power back-off value: about 7dB backed off from the 1dB compression point). The RF output power corresponding to the 1dB compression point (P1dB) is set at 20dBm. The receiving channel needs to achieve a noise figure of less than 4dB (including switching loss) at very low current consumption (maximum 15mA, +4V power supply).

　　The functional block diagram of the RF front-end MMIC is shown in Figure 1. The transmit signal path extends from the left to the right in the upper half of the figure; the input port is located on the pin labeled "PA_RFin". The input signal is amplified by a three-stage power amplifier (PA) and then connected to the antenna through an RF power detector and a single-pole double-throw (SPDT) switch. The on-chip directional power detector monitors the transmitted RF output power, and temperature compensation is integrated on the chip. The compensated power detector output is determined by the difference between the voltage "Vref" and the voltage "Vdet". A fast switching enable circuit (PA enable circuit in Figure 1) controlled by the (active low) logic signal "PA_ON" is integrated in the chip. The PA can be quickly powered on and off when switching between transmit and receive modes, so that only 0.1mA of current is used when the PA is not in use, maximizing the efficiency of the entire system.

Figure 1: Functional block diagram of a
　　28GHz 5G communication RF front-end module chip

　　The PA is usually operated a few dB backed off from the compression point to keep the modulated signal it transmits from being severely distorted. The design approach is to optimize the performance of the power amplifier operating at about 7 dB backed off from the P1dB point. In order to achieve a better PAE under this operating condition, the PA will be biased in deep class AB.

　　2. Design compromise strategy

　　The design starts with device-level simulation of candidate unit transistors. This simulation can obtain key information such as device size, bias point, target impedance, PA level and driver ratio, laying a solid foundation for subsequent fine power amplifier design.

　　An important part of this work is to determine how to maximize PAE under power back-off. Generally speaking, this is achieved by reducing the device static bias current density. However, the range to which the current density can be reduced in this approach is limited by gain and linearity constraints, as both deteriorate with reduced current density. There is a clear trade-off relationship between PAE under power back-off conditions and gain and linearity.

　　The main linearity specification of concern in the design is that IMD3 must be less than -35dBc under power back-off conditions. As shown in Figure 2, the IMD3 performance is particularly sensitive to the fundamental frequency load conditions when the bias current is reduced. Figure 2a shows the load-pull simulation results of an 8×50μm device biased in deep class AB at 4V and 75mA/mm, and marks the load corresponding to the PAE optimal point under P1dB. The figure also shows the performance of IMD3 under the optimal load and power back-off conditions obtained by simulation, indicating that there is about 4dB margin from the -35dBc specification. The simulated PAE is about 15% under this power back-off condition, and this efficiency only takes into account the role of the device and does not include any output loss. Figure 2b shows the load corresponding to the P1dB power optimal point and IMD3 information under the same device and bias working conditions. It is found that under the same relative power back-off conditions, its IMD3 performance is significantly worse, exceeding the specification by more than 5dB, while the PAE is similar to the previous condition, about 15.7%.

Figure 2: Impedance point corresponding to the best PAE at P1dB and the
　　corresponding IMD3 at power back-off (a). Impedance point corresponding to the best power at P1dB and the corresponding IMD3 at power back-off (b).

　　The performance of the power amplifier under P1dB and power back-off conditions at other impedance points on the Smith chart was further evaluated. The load condition in Figure 2a clearly has the best overall performance and was therefore selected for the output stage design. A bias current of 52mA/mm was ultimately selected, and an 8x50μm device was selected as the basic unit of the output stage to meet the power index requirements. The need for three-stage amplification was determined based on the total transmission gain index.