Development of image processing system based on TMS320C6657 dual-core DSP

火辣西米秀

Development of image processing system based on TMS320C6657 dual-core DSP [Copy link]

1. Introduction

In the new project, we plan to upgrade the existing TMS320C6455+Kintex7 FPGA platform and use TMS320C6657 as the new core. The following points are taken into consideration:

1) With DDR3 interface, image processing algorithms can be transplanted more conveniently without being limited by the size of on-chip L2 space;

2) Dual-core DSP, which can realize more functions;

3) Compared with C6455, it is a new generation process with higher energy consumption ratio.

This article mainly contains several tips in the hardware design process.

2. Tips 1: Flash

EMIF16 is the external memory control interface of C6657, which can realize seamless connection with various asynchronous memories such as ASRAM, NOR FLASH and NAND FLASH memory. It only has asynchronous transmission mode. The data bit width of EMIF16 interface of C6657 is 16 bits, the address bit width is 24 bits, and the chip select is CE0~CE4.

1) If NAND Flash is selected as the program memory, since the 8/16-bit IO port can be reused as a data/address/command transmission channel, it can not only reduce the number of PINs, but also ensure interface compatibility between devices of different capacities, and there is no need to change the design when upgrading the storage capacity. The connection methods of 8-bit and 16-bit are as follows:

NAND Flash models are often selected from SLC NAND Flash Devices produced by Micron, but it is not recommended to use 50-series (50nm) series devices. Instead, you should choose the required capacity from 60-series (34nm) series devices. In terms of process, ECC function, supported commands, performance, etc., the 60 series is better than the 50 series. If you refer to the EVM board for schematic design, pay attention to updating the model of its onboard NAND FLASH as follows:

2) Nor Flash

When using Nor Flash, you need to pay attention to the connection sequence of the EMIFA signal and the Nor Flash address signal. The 8-bit/16-bit mode is different. For the 16-bit mode, EMIFA23 should be connected to A0 of Nor Flash; and for the 8-bit mode, EMIFA[23:22] is connected to A[1:0] of Nor Flash, as shown in the figure below. If there are any sequence requirements for the data lines, refer to the Flash Datasheet used.

3. Tips 2: boot configuration

The boot configuration of C6657 is controlled by GPIO[15:0]. The conventional method is to set the Pull Up/Pull Down resistors to form a configuration matrix and set the boot mode by selective soldering. The disadvantage is that it takes up a certain PCB area.

The board designed this time contains an Artix 7 series FPGA with 250 user IOs. The DSP's GPIO[15:0] is connected to the unused IO of the FPGA, and the FPGA controls the DSP's startup mode. This method has two key points:

1) The BANK of FPGA must be 1.8V, otherwise a level conversion chip needs to be added;

2) When the DSP's POR is deasserting, it is important to ensure that the FPGA has been loaded and given the correct GPIO configuration value, otherwise the DSP cannot start normally. This can be achieved by cascading the "AND gate" chip into a reset chain for the entire board, that is, the cascade relationship:

PWR GOOD ---> FPGA boot complete ---> FPGA working --->DSP POR deassert;

Or the FPGA can uniformly control the reset timing relationship of the entire board chip.

4. Tips 3: Clock circuit

The clock input frequency range and types supported by C6657 are as follows:

1) C6657 has a built-in parallel terminal resistor of 100Ω, so AC coupling must be used.

2) For unused clock input pins, connect them to a suitable power rail to ensure a stable voltage. The official recommendation is to add a 1k pull-down resistor to reduce power consumption, as shown below:

The power supplies that can be connected are as follows:

3) Place the AC coupling capacitor as close to the DSP end as possible;

4) The clock is required to be valid before POR is pulled high; however, the clock terminal must be in high impedance state before CVDD is valid.

5. Tips 4: Startup configuration and initialization

GPIO[0:15] is used to configure the system startup mode. It is generally set by pull-up/pull-down resistors or FPGA. The external resistance capacity is different according to the default pull-up and pull-down configuration inside the device: if the external pull-up level is the same as the internal default pull-up level, a 4.7k resistor is used; otherwise, a 1k resistor is used; according to the device manual, only GPIO[0] is internally pulled up, and GPIO[1:15] are all internally pulled down. Therefore, for GPIO[0], 4.7k is used for external pull-up and 1k is used for pull-down; while for GPIO[1:15], a 1k resistor is required for external pull-up and a 4.7k resistor is required for pull-down.

The boot mode and other device configurations are latched on the rising edge of the RESETFULL pin. Once the values on these pins are latched into the configuration registers, they become available as user IOs.

6. Tips 5: Reset sequence

1) POR:

During the power-on process and before the clock is valid, it must remain low. At this time, almost all outputs are in Hi-Z state.
RESET is released before POR;
the internal circuit of POR cannot detect the effectiveness of the power system, so before releasing POR, it is necessary to ensure that the power supply is normal.
Generally, a voltage monitoring circuit is used to pull down POR after detecting that the DSP power supply fails to prevent overcurrent from burning the device.
2)ResetFull

Used to reset the internal configuration register to the default value, the function is similar to POR. It is required that ResetFull lags behind the release of POR/RESET. When POR is pulled low, RESERFULL is required to be pulled low at the same time.

3) Reset

Reset does not latch the boot configuration and other configurations, nor does it reset the related data that has been latched internally.

7. Tips 6: About SmartReflex

For KeyStone devices such as C6657, CVDD is adjustable. The actual voltage value of CVDD can vary within a certain range, and each device is different, so for the power supply of CVDD, SmartReflex-compliant circuits must be used. Initially, it is set to 1.1V and then adjusted to the value required by the device by the SmartRefex circuit.

Each device is produced and tested by the manufacturer to determine a set of codes that identify the ideal voltage values:

After the test is completed, the code corresponding to the lowest acceptable voltage of the device is permanently written into the device. This 6-bit code, called the VID (Voltage Identification) value, represents the optimized voltage of the device.

The VCNTL[3:0] pins of each device are used to transmit 6-bit code to the SmartReflex circuit. This group of pins is OD output and needs to be connected to a 4.7k pull-up resistor to DVDD1V8. Note: this transition will occur only a single time after a power-up reset has occurred. A detailed description of it is as follows:

The falling edge of VIDS latches in the data from VIDC, VIDB, and VIDA as the lower three LSB of the IDAC value. After a
minimum hold time, the rising edge of VIDS latches in the data from VIDC, VIDB, and VIDA as the upper three LSB of the IDAC value . Four pins are used to communicate with the LM10010. VIDC, VIDB, and VIDA are data lines, while VIDS is a latching strobe that programs in the LM10010 data. As shown in the Timing Diagram in Figure 2 , the falling edge of VIDS latches in the data from VIDC, VIDB, and VIDA as the lower three LSB of the IDAC value. After a minimum hold time, the rising edge of VIDS latches in the data from VIDC, VIDB, and VIDA as the upper three LSB of the IDAC value. Internally, a delay on VIDS allows for the setting of all VID lines simultaneously.The VID data word is set so that the lowest output current is seen at the highest VID data word (59.2 A at a code of 0d). Conversely, the lowest current is seen at the highest VID data word (0 A at 63d). During VID operation with the regulator, this will translate to the lowest output voltage with the lowest VID word, and the highest output voltage with the highest VID word. The communications pins can be used with a low voltage microcontroller, with a maximum VIL of 0.4V and a minimum VIH of 1.1V. Upon startup, the IDAC is set at a code of 46d, which translates to approximately 16 A. This default startupvalue is trimmed at final test.

Summary: With power supply, clock, correct reset sequence and FLASH, C6657 has a normal working environment and can be connected to the emulator for debugging. Other peripherals can be added according to system requirements. In the image processing system, it is generally necessary to add a set of DDR3 as image cache and open the SRIO interface as image