3946 views|15 replies

8

Posts

0

Resources
The OP
 

Why is the output waveform of Quartus 13.0 always at a low level? [Copy link]

 
Newbie asks for advice
This post is from FPGA/CPLD

Latest reply

The simulation time is too short. The output flips once after 24999999 clocks. You didn't simulate for that long.  Details Published on 2019-4-28 15:00
 

2113

Posts

0

Resources
2
 
Your first line is 2HZ and the third line is 1Hz. The two names are different. Is there no error?
This post is from FPGA/CPLD
 
 

2113

Posts

0

Resources
3
 
Have you used quartus to compile? If you did, there should be at least a warning. This problem is likely to occur when you start writing.
This post is from FPGA/CPLD
 
 
 

8

Posts

0

Resources
4
 
heningbo posted on 2019-4-8 08:43 Your first line is 2HZ and the third line is 1Hz. The two names are different. Is there no error?
It's still the same after changing it. It may be a software problem.
This post is from FPGA/CPLD

Comments

It shouldn't be a software problem. What software did you use to simulate it and what did you change it to? Please post it and let us know.  Details Published on 2019-4-8 16:04
 
 
 

2113

Posts

0

Resources
5
 
Snot Beast posted on 2019-4-8 11:15 It's still the same after changing it. It may be a software problem.
It shouldn't be a software problem. What software did you use to simulate it and what did you change it to? Please post it and let us know.
This post is from FPGA/CPLD
 
 
 

2113

Posts

0

Resources
6
 
Try to write this program. If it still doesn't work, I can't help you.module XX( input clk, output reg clk_1hz ); reg [24:0] cnt; always@(posedge clk)begin if(cnt == 25'd24_999_999) cnt <= 25'd0; else cnt <= cnt + 25'd1; end always@(posedge clk)begin if(cnt == 25'd24_999_999) clk_1hz <= ~clk_1hz; else clk_1hz <= clk_1hz; end endmodule
This post is from FPGA/CPLD
 
 
 

216

Posts

0

Resources
7
 
After Quartus II9.0, simulation must use the separately installed moalsim simulation software, and also write Testbench test files.
This post is from FPGA/CPLD
 
 
 

8

Posts

0

Resources
8
 
heningbo posted on 2019-4-8 16:04 It shouldn't be a software problem. What software did you use to simulate and what did you change it to? Please post it and let me see
I used VWF simulation and tried your program and the result was the same  
This post is from FPGA/CPLD
 
 
 

8

Posts

0

Resources
9
 
LuJianchang posted on 2019-4-9 09:08 After Quartus II 9.0, simulation must use the separately installed moalsim simulation software, and also write Testbench test files.
Can't use the built-in simulation software?
This post is from FPGA/CPLD

Comments

Well, since 9.0, it has been joint simulation  Details Published on 2019-4-10 08:54
Well, since 9.0, it has been joint simulation  Details Published on 2019-4-10 08:32
 
 
 

216

Posts

0

Resources
10
 
Posted by Snot Beast on 2019-4-9 16:36 Can't use the built-in simulation software?
Well, since 9.0, it has been joint simulation.
This post is from FPGA/CPLD
 
 
 

216

Posts

0

Resources
11
 
Posted by snotbeast on 2019-4-9 16:36 Can't use the built-in simulation software?
Modelsim simulation process: https://blog.csdn.net/sunlinyi66/article/details/41279953 Quartus II 15 installation and cracking tutorial: https://blog.csdn.net/yxswhy/article/details/79612383
This post is from FPGA/CPLD
 
 
 

8

Posts

0

Resources
12
 
LuJianchang published on 2019-4-10 08:54 Modelsim simulation process: https://blog.csdn.net/sunlinyi66/article/details/41279953 quartus ii 15 installation and breaking...
Thank you brother
This post is from FPGA/CPLD
 
 
 

122

Posts

0

Resources
13
 
Yours is a simulation. If the counter has no initial value, it cannot be simulated. If you call the counter, it should have no value
This post is from FPGA/CPLD
 
 
 

8

Posts

0

Resources
14
 
Hao Xushuai published on 2019-4-14 10:59 Your simulation is for simulation. If the counter has no initial value, it cannot be simulated. You can check the counter. There should be no value...
Yes, I ignored this problem. Thank you, brother.
This post is from FPGA/CPLD
 
 
 

1

Posts

0

Resources
15
 
The simulation time is too short. The output flips once after 24999999 clocks. You didn't simulate for that long.
This post is from FPGA/CPLD
 
 
 

8

Posts

0

Resources
16
 
342141234242342 Published on 2019-4-28 15:00 The simulation time is too short. The output flips once after 24999999 clocks. You didn't simulate for such a long time
What parameters need to be adjusted during simulation?
This post is from FPGA/CPLD
 
 
 

Guess Your Favourite
Find a datasheet?

EEWorld Datasheet Technical Support

Related articles more>>
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号
快速回复 返回顶部 Return list