Why can't quartus simulate the waveform? Can you help me take a look?

小孩彦旻旻

Why can't quartus simulate the waveform? Can you help me take a look? [Copy link]

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Top-level modules

DDS sine wave signal generator module

module dds_noip(
input wire sclk,
input wire rst_n,
input wire [7:0] FW,
output wire [7:0] o_wave,
output reg out
);

parameter FRQ_W=32'd85899346; //equivalent to M
parameter FRQ_ADD=32'd85899346/2; //equivalent to increment
reg [31:0] phase_sum;
wire [8:0] addr;
reg [31:0] frq_word;
reg [6:0] div_cnt;
reg div_flag;

always @(posedge sclk or negedge rst_n)
if(rst_n == 1'b0)
phase_sum <= 1'd0;
else
phase_sum <= phase_sum + FRQ_W/FW;

assign addr = phase_sum[31:23];

always @(posedge sclk or negedge rst_n)
if(rst_n == 1'b0)
out <= 0;
else if(o_wave>128)
out <= 1;
else
out <= 0;

rom_512x8 rom_512x8_inst(
.address(addr),
.clock(sclk),
.rst(rst_n),
.q(o_wave)
);

endmodule

rom module

module rom_512x8 (
address,
clock,
rst,
q
);
input [8:0] address;
input clock;
input rst;
output reg [7:0] q;

parameter SINE_FILE = "sine.txt";

reg [7:0] sine_rooms [511:0];

initial
begin
$readmemh(SINE_FILE, sine_rom);
end

always@(posedge clock,negedge rst)
begin

if(!rst)
begin
q<=8'b0;
end

else
begin
q<=sine_rom[address];
end

end

endmodule

UART serial port receiving module

module uart_rx(
clk,
res,
RX,
data_out,
en_data_out
);

input clk;
input res;
input RX;
output[7:0] data_out;//Receive byte
output output en_data_out;//Output enable

reg[7:0] state;//Main state machine
reg[12:0] con;//Used to calculate the bit width;
//System clock frequency 24 MHz (24,000,000), support 4800 baud rate
//Count 24000000/4800=5000 (0001 0011 1000 1000), 13 bits
//1.5 times width, 5000*1.5=7500, count 8000 (0001 1111 0100 0000), 13 bits
reg[4:0] con_bits;//Used to calculate the number of bits, count how many revolutions

reg RX_delay;//RX delayreg
en_data_out;

reg[7:0] data_out;

always@(posedge clk or negedge res)

if(~res)begin
state<=0;con<=0;con_bits<=0;RX_delay<=0;
data_out<=0;en_data_out<=0;
end
else begin

RX_delay<=RX;//Moving as long as there is a clock, no condition required


case(state)
0://Wait for idle, more than 10 bits are continuous 1
begin
if(con==5000-1)begin
con<=0;//Counting has gone around
end
else begin
con<=con+1;
end
if(con==0)begin
if(RX)begin
con_bits<=con_bits+1;
end
else begin
con_bits<=0;
end
end

if(con_bits==12)begin
state<=1;
end
end

1://Wait for the start bit;
begin
en_data_out<=0;
if(~RX&RX_delay)begin
state<=2;
end
end
2://Receive the lowest bit b0;
begin
//Wait for 1.5Tbit, 5000*1.5=7500
if(con==7500-1)begin
con<=0;
data_out[0]<=RX;
state<=3;
end
else begin
con<=con+1;
end
end
3://Receive the lowest bit b1;
begin
//Wait for 1Tbit, 5000*1=5000
if(con==5000-1)begin
con<=0;
data_out[1]<=RX;
state<=4;
end
else begin
con<=con+1;
end
end
4://Receive the lowest bit b2
begin
//Wait for 1Tbit, 5000*1=5000
if(con==5000-1)begin
con<=0;
data_out[2]<=RX;
state<=5;
end
else begin
con<=con+1;
end
end
5://Receive the lowest bit b3
begin
//Wait for 1Tbit, 5000*1=5000
if(con==5000-1)begin
con<=0;
data_out[3]<=RX;
state<=6;
end
else begin
con<=con+1;
end
end
6://Receive the lowest bit b4
begin
//Wait for 1Tbit, 5000*1=5000
if(con==5000-1)begin
con<=0;
data_out[4]<=RX;
state<=7;
end
else begin
con<=con+1;
end
end
7://Receive the lowest bit b5
begin
//Wait for 1Tbit, 5000*1=5000
if(con==5000-1)begin
con<=0;
data_out[5]<=RX;
state<=8;
end
else begin
con<=con+1;
end
end
8://Receive the lowest bit b6
begin
//Wait for 1Tbit, 5000*1=5000
if(con==5000-1)begin
con<=0;
data_out[6]<=RX;
state<=9;
end
else begin
con<=con+1;
end
end
9://Receive the lowest bit b7
begin
//Wait for 1Tbit, 5000*1=5000
if(con==5000-1)begin
con<=0;
data_out[7]<=RX;
state<=10;
end
else begin
con<=con+1;
end
end
10://Generate enable pulse
begin
en_data_out<=1;
state<=1;
end

default://Other undefined states
begin
state<=0;
con<=0;
con_bits<=0;
en_data_out<=0;

end


endcase

end

endmodule

The rom initialization files are also placed in the same directory as db and modelsim, but there is still no problem. Is it a problem with the module connection?