Home > 555 Circuits >555-Delay Timer Circuits > The power-on delay output low level circuit composed of NE555

The power-on delay output low level circuit composed of NE555

Source: InternetPublisher:赔钱虎 Keywords: NE555 delay circuit Updated: 2024/10/17

The power-on delay output low level circuit is shown in the figure below. When the circuit is connected to the power supply, since the capacitor C has no time to charge, the ② and ⑥ pins of the 555 time base circuit are at a low level, and the ③ pin outputs a high level. As the capacitor C charges, the potential of the ② and ⑥ pins of the 555 time base circuit begins to rise. When the potential of the ② pin rises to 2/3 Vcc, the circuit state flips, and the ③ pin changes from a high level to a low level and remains there. The delay time tw=1.1RC. This circuit is often used to control the local circuit in the whole circuit to stop working by disconnecting the power supply after a certain period of time of power-on.

The power-on delay output low level circuit composed of NE555

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

About Us Customer Service Contact Information Datasheet Sitemap LatestNews


Room 1530, 15th Floor, Building B, No.18 Zhongguancun Street, Haidian District, Beijing, Postal Code: 100190 China Telephone: 008610 8235 0740

Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号