The power-on delay output low level circuit composed of NE555

The power-on delay output low level circuit is shown in the figure below. When the circuit is connected to the power supply, since the capacitor C has no time to charge, the ② and ⑥ pins of the 555 time base circuit are at a low level, and the ③ pin outputs a high level. As the capacitor C charges, the potential of the ② and ⑥ pins of the 555 time base circuit begins to rise. When the potential of the ② pin rises to 2/3 Vcc, the circuit state flips, and the ③ pin changes from a high level to a low level and remains there. The delay time tw=1.1RC. This circuit is often used to control the local circuit in the whole circuit to stop working by disconnecting the power supply after a certain period of time of power-on.