PCB Layout Guidelines

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PCB Layout Guidelines Step 1: Determine the Current Path

In a switching converter design, high-current paths and low-current paths are placed in close proximity to each other. The AC path carries spikes and noise, the high DC path produces a considerable voltage drop, and the low-current path is often sensitive to noise. The key to proper PCB layout is to identify the critical paths, then arrange the components and provide enough copper area to prevent the high current from destroying the low current. Poor performance is manifested by ground bounce and noise injection into the IC and the rest of the system.

Figure 1 shows a synchronous buck regulator design that includes a switching controller and the following external power components: high-side switch, low-side switch, inductor, input capacitor, output capacitor, and bypass capacitor. The arrows in Figure 1 indicate where the high switch current flows. These power components must be carefully placed to avoid undesirable parasitic capacitance and inductance that can cause excessive noise, overshoot, ringing, and ground bounce.

Figure 1. Typical switching regulator (showing AC and DC current paths)

The switching current paths such as DH, DL, BST, and SW need to be carefully arranged after leaving the controller to avoid excessive parasitic inductance. These lines carry high δI/δt AC switching pulses that can reach more than 3 A and last for nanoseconds. The high current loop must be small to minimize output ringing and avoid picking up additional noise.

Low-value, low-amplitude signal paths, such as compensation and feedback devices, are sensitive to noise. These paths should be kept away from switch nodes and power devices to avoid injecting interfering noise.

Step 2: Layout Physical Planning

PCB physical planning (floor plan) is very important. The current loop area must be minimized and the power devices must be arranged properly to allow current to flow smoothly, avoiding sharp corners and narrow paths. This will help reduce parasitic capacitance and inductance, thereby eliminating ground bounce. Figure 2 shows the PCB layout of a dual-output buck converter using the ADP1850 switching controller. Note that the layout of the power components minimizes the current loop area and parasitic inductance. The dashed lines indicate the high current paths. Both synchronous and asynchronous controllers can use this physical planning technique. In the asynchronous controller design, a Schottky diode replaces the low-side switch. Figure 2. PCB layout of a dual-output buck converter using the ADP1850 controller. BlinkMacSystemFont, "] The current waveform at the top and bottom power switches is a pulse with very high δI/δt. Therefore, the path connecting each switch should be as short as possible to minimize the noise picked up by the controller and the noise transmitted by the inductive loop. When using a pair of DPAK or SO-8 packaged FETs on one side of the PCB, it is best to rotate the two FETs in opposite directions so that the switch node is on one side of the pair and use suitable ceramic bypass capacitors to bypass the high-side leakage current to the low-side source. Be sure to place the bypass capacitors as close to the MOSFETs as possible (see Figure 2) to minimize the inductance around the loop through the FETs and capacitors.

The placement of the input bypass capacitors and the input bulk capacitors is critical to controlling ground bounce. The negative terminal of the output filter capacitor should be connected as close as possible to the source of the low-side MOSFET. This helps to reduce the loop inductance that causes ground bounce. Cb1 and Cb2 in Figure 2 are ceramic bypass capacitors. The recommended value range for these capacitors is 1 μF to 22 μF. For high current applications, an additional larger value filter capacitor should be connected in parallel, as shown as CIN in Figure 2.