How to start with PCB layout and wiring to avoid noise caused by improper switching power supply layout

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"Noise problem!" - These are the four words every PCB designer will hear. In order to solve the noise problem, it is often necessary to spend hours on laboratory testing to find the culprit, but in the end it is found that the noise is caused by improper layout of the switching power supply. Solving such problems may require designing a new layout, resulting in product delays and increased development costs.

This article will provide guidelines for printed circuit board (PCB) layout to help designers avoid such noise problems. Using the ADP1850 dual-channel synchronous switching controller as an example, the first step in the switching regulator layout is to determine the current path of the regulator. The current path then determines the location of the device in this low-noise layout design.

PCB Layout Guidelines

Step 1: Determine the current path

In a switching converter design, high current paths and low current paths are placed very close to each other. The AC path carries spikes and noise, the high DC path produces a considerable voltage drop, and the low current path is often sensitive to noise. The key to proper PCB layout is to identify the critical paths, then arrange the components and provide enough copper area to prevent the high current from destroying the low current. Poor performance is manifested in ground bounce and noise injection into the rest of the IC and the system.

Figure 1 shows a synchronous buck regulator design that includes a switching controller and the following external power components: high-side switch, low-side switch, inductor, input capacitor, output capacitor, and bypass capacitor. The arrows in Figure 1 indicate where the high switch currents flow. These power components must be carefully placed to avoid undesirable parasitic capacitance and inductance that can cause excessive noise, overshoot, ringing, and ground bounce.

Figure 1. Typical switching regulator (showing AC and DC current paths)

Switching current paths such as DH, DL, BST, and SW need to be carefully arranged after leaving the controller to avoid excessive parasitic inductance. These lines carry high δI/δt AC switching pulse currents that can reach more than 3 A and last for nanoseconds. The high current loop must be small to minimize output ringing and avoid picking up additional noise.

Low-value, low-amplitude signal paths, such as compensation and feedback devices, are sensitive to noise. These paths should be kept away from switch nodes and power devices to avoid injecting interfering noise.

Step 2: Layout Physical Planning

PCB physical planning (floor plan) is very important. The current loop area must be minimized and the power components must be arranged properly to allow the current to flow smoothly, avoiding sharp corners and narrow paths. This will help reduce parasitic capacitance and inductance, thereby eliminating ground bounce.

Figure 2 shows the PCB layout of a dual-output buck converter using the ADP1850 switching controller. Note that the layout of the power components minimizes the current loop area and parasitic inductance. The dashed lines indicate the high current paths. Both synchronous and asynchronous controllers can use this physical planning technique. In the asynchronous controller design, the Schottky diode replaces the low-side switch.

Figure 2. PCB layout of a dual-output buck converter using the ADP1850 controller.

Step 3: Power Devices - MOSFETs and Capacitors (Input, Bypass, and Output)

The current waveform at the top and bottom power switches is a pulse with very high δI/δt. Therefore, the path connecting each switch should be as short as possible to minimize the noise picked up by the controller and the noise transmitted by the inductive loop. When using a pair of DPAK or SO-8 packaged FETs on one side of the PCB, it is best to rotate the two FETs in opposite directions so that the switch node is on one side of the pair of FETs and bypass the high-side leakage current to the low-side source with a suitable ceramic bypass capacitor. Be sure to place the bypass capacitor as close to the MOSFET as possible (see Figure 2) to minimize the inductance around the loop through the FET and capacitor.

The placement of the input bypass capacitor and the input bulk capacitor is critical to controlling ground bounce. The negative terminal of the output filter capacitor should be connected as close as possible to the source of the low-side MOSFET, which helps reduce the loop inductance that causes ground bounce. Cb1 and Cb2 in Figure 2 are ceramic bypass capacitors, and the recommended value range for these capacitors is 1 μF to 22 μF. For high current applications, an additional larger value filter capacitor should be connected in parallel, as shown by CIN in Figure 2.

Thermal Considerations and Ground Planes

Under heavy load conditions, the equivalent series resistance (ESR) of the power MOSFET, inductor, and large capacitor will generate a lot of heat. In order to effectively dissipate the heat, the example in Figure 2 places a large area of copper under these power devices.

Multi-layer PCBs dissipate heat better than 2-layer PCBs. To improve heat dissipation and conductivity, use 2-ounce copper on top of the standard 1-ounce copper layer. Connecting multiple PGND layers together with vias can also help. Figure 3 shows a 4-layer PCB design with PGND layers on the top, third, and fourth layers.

Figure 3. Cross-sectional view: Connecting the PGND plane to improve heat dissipation.

This multi-ground plane approach isolates noise-sensitive signals. As shown in Figure 2, the negative terminals of the compensation components, soft-start capacitors, bias input bypass capacitors, and output feedback divider resistors are all connected to the AGND plane. Do not connect any high current or high δI/δt paths directly to the isolated AGND plane. AGND is a quiet ground plane where no high current flows.

The negative terminals of all power components (such as low-side switches, bypass capacitors, input and output capacitors, etc.) are connected to the PGND plane, which carries high current.

The voltage drop in the GND plane can be significant enough to affect the output accuracy. Connecting the AGND plane to the negative terminal of the output capacitor via a wide trace (see Figure 4) can significantly improve the output accuracy and load regulation.

Figure 4. Connection of AGND layer to PGND layer

The AGND layer extends all the way to the output capacitor, and the AGND layer and the PGND layer connect to the via at the negative end of the output capacitor.

Figure 2 shows another technique for connecting the AGND and PGND layers, where the AGND layer is connected to the PGND layer through a via near the negative terminal of the output bulk capacitor. Figure 3 shows a cross section of a location on the PCB, where the AGND and PGND layers are connected through a via near the negative terminal of the output bulk capacitor.

Current sensing path

To avoid interference noise causing accuracy degradation, the current sensing path layout of the current mode switching regulator must be appropriate. Dual-channel applications require special attention to eliminate any crosstalk between channels.

The dual-channel buck controller ADP1850 uses the on-resistance RDS(ON) of the low-side MOSFET as part of the control loop architecture. This architecture senses the current flowing through the low-side MOSFET between the SWx and PGNDx pins. Ground current noise in one channel may couple into the adjacent channel. Therefore, it is important to keep the SWx and PGNDx traces as short as possible and place them close to the MOSFETs for accurate current sensing. The connections to the SWx and PGNDx nodes must use the Kelvin sensing technique as shown in Figure 2 and Figure 5. Note that the corresponding PGNDx trace is connected to the source of the low-side MOSFET. Do not arbitrarily connect the PGND plane to the PGNDx pin.

Figure 5. Grounding techniques for two channels.

In contrast, for dual-channel voltage-mode controllers such as the ADP1829, the PGND1 and PGND2 pins are connected directly to the PGND plane through vias.

Feedback and current limit sensing paths

The feedback (FB) and current limit (ILIM) pins are low signal level inputs, therefore, they are sensitive to capacitive and inductive noise interference. Avoid routing the FB and ILIM traces close to high δI/δt traces. Be careful not to allow the traces to form loops, which can add undesirable inductance. Adding a small MLCC decoupling capacitor (such as 22 pF) between the ILIM and PGND pins can help filter the noise further.

Switch Node

In a switching regulator circuit, the switch (SW) node is the noisiest location because it carries large AC and DC voltages/currents. This SW node requires a large copper area to minimize resistive voltage drops. Placing the MOSFET and inductor close to each other on a copper plane minimizes series resistance and inductance.

Applications that are more sensitive to EMI, switch node noise, and ringing can use a small snubber. A snubber is a resistor and capacitor in series (see RSNUB and CSNUB in Figure 6) placed between the SW node and the PGND plane to reduce ringing and EMI on the SW node. Note that adding a snubber may slightly reduce overall efficiency by 0.2% to 0.4%.

Figure 6. Buffer and gate resistors

Gate driver path

The gate drive traces (DH and DL) also deal with high δI/δt, which tends to produce ringing and overshoot. These traces should be as short as possible. It is best to route them directly and avoid using feedthrough vias. If vias must be used, use two vias per trace to reduce peak current density and parasitic inductance.

A small resistor (about 2 Ω to 4 Ω) in series with the DH or DL pin can slow down the gate drive, which can also reduce gate noise and overshoot. Alternatively, a resistor can be connected between the BST and SW pins (see Figure 6). Reserving space with a 0 Ω gate resistor during layout allows for greater flexibility for later evaluation. The added gate resistor increases the gate charge rise and fall times, resulting in higher switching power losses in the MOSFET.

Summarize

Understanding the current paths, their sensitivity, and proper device placement are key to eliminating noise issues in PCB layout design. All of ADI's power device evaluation boards use the above layout guidelines to achieve optimal performance. The evaluation board files UG-204 and UG-205 detail the layout associated with the ADP1850.

Note that all switching power supplies have the same components and similar current path sensitivities. Therefore, the guidelines described using the ADP1850 as an example for a current-mode buck regulator also apply to the layout of voltage-mode and/or boost switching regulators.

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