Optimization of Complex Multipliers in Embedded Development FPGA[Copy link]
In digital signal processing, especially in communication signal processing applications, complex multipliers are often encountered. Some friends may feel strange, the signals are all real signals, where do complex numbers come from? In fact, in communication signals, the baseband signal will be divided into I and Q, and then modulated using QPSK/DQPSK. After demodulation at the receiving end, two signals will be obtained. So generally speaking, for the convenience of representation and operation, the I signal is generally regarded as the real part and the Q signal as the imaginary part. For example, after the input signal (I and Q) is transformed into a frequency signal (with real and imaginary parts) by FFT, it is represented as a+b*i and another complex number (cosx+sinx*i, represented as c+d*i) for multiplication, which is equivalent to the phase shift of the I and Q signals in the time domain. Then the complex multiplier is used at this time. At a glance, a complex multiplier requires 4 multipliers and 3 adders (subtraction is actually complement addition): (a+b*i)*(c+d*i) = (a*c - b*d) + (b*c + a*d)*i = x + y*i But the formula can be simplified to: where x is equivalent to a*c - b*d + (b*c - a*d) - (b*c - a*d) So it is simplified to a*c - b*c + a*d - b*d + (b*c - a*d) = (c+d)*(ab) + (b*c - a*d) = Since the calculation of x already includes the results of b*c and a*d, we only need to calculate x to calculate y. It only takes 3 multipliers to calculate x. This saves one multiplier. If the FPGA's DSP48 is used as a multiplier, this optimization method is very effective because one of the DSP48s is saved. Of course, if Xilinx's IPCORE is used and DSP48 is used to implement a complex multiplier, the multiplier generated by Xilinx is also similar to this architecture. However, if it is designed in ASIC or LUT is used to implement the multiplier, then this architecture may not save resources.