How to optimize the area of FPGA design

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How to optimize the area of FPGA design [Copy link]

1. When the speed requirement is not very high, we can design the pipeline in an iterative form to reuse the resources with the same FPGA function. 2. When the control logic is smaller than the shared logic, the control logic resources can be reused. For example, in the implementation of the FIR filter, the multiplier is a shared resource. We can use the control resource to implement the state machine, thereby reusing the multiplier. Of course, this also sacrifices the area. 3. For modules with similar counting units, a global counter can be used to reduce the area. For example, module A requires a cycle count of 256 and module B requires a cycle count of 1000. Then we can design a global counter with 10 bits. The first eight bits are used for module A and the entire counter is used for B. Reasonable use of PLL for frequency division can achieve a more flexible global counter design. 4. Not all internal logic resources of the FPGA support reset (synchronous reset, asynchronous reset), set, etc. Improper reset position will increase resource overhead. For example, DSP and RAM only support synchronous reset. Reset is not supported for shift registers, and set is not supported for multipliers. 5. Using set and reset can achieve some combinational logic optimization; for example, for A|B, we can connect A directly to the input of the trigger, and connect B to the set section of the trigger, thus saving an OR gate. 6. For circuits with tight area requirements, reset and set should be avoided as much as possible .

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How to optimize the area of FPGA design

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