S/PDIF (Sony/Philips Digital Interface) is a high-quality digital audio format commonly used in consumer electronics for interconnection of audio devices. Many audio codecs/DSPs only support I2S ^as digital audio input/output, which can cause problems when using these devices in circuits that need to support both S/PDIF and AES (Audio Engineering Society) professional standards.

The circuit shown in Figure 1 solves this problem by connecting the ADAV801 or ADAV803 audio codec to a SigmaDSP® device such as the ADAU1761 .

The audio input in S/PDIF format is first converted to I ² S format, and then processed by ADAU1761. The processed I ² S format audio output is then converted back to S/PDIF format by ADAV801/ADAV803. The ADAV801/ADAV803 features a flexible digital input/output routing matrix that can handle audio in I ² S or S/PDIF formats and output in either format; utilizing an on-chip SRC (sample rate converter), it can be used as Master or slave. ADAV801/ADAV803 supports consumer audio standards, and channel status data can be embedded in the audio stream by writing to the relevant registers in ADAV801/ADAV803. This feature can be used to transfer configuration information between devices. ADAV801/ADAV803 has a stereo DAC/ADC, which can also be used to process audio when needed.

ADAV801/ADAV803 has 2 sets of input/output I ² S ports, any set can be used. In the configuration shown in Figure 1, the playback port ILRCLK pin and the recording port OLRCLK pin are connected to the LRCLK pin of the ADAU1761. The IBCLK and OBCLK pins are connected to the BCLK pin of the ADAU1761. The ISDATA pin is connected to the ADC_SDATA pin of the ADAU1761, and the OSDATA pin is connected to the DAC_SDATA pin of the ADAU1761.

The S/PDIF input comes from the TORX173 fiber optic receiver module, going to the DIRIN pin, and then output in I2S ^format through the recording port to the ADAU1761. After the audio is processed by the ADAU1761 SigmaDSP® device, it is output to the playback port of the ADAV801/ADAV803 in I2S format through the ADC_SDATA pin, then converted to S/PDIF format and fed into the TOTX173 optical transmitter module through the DITOUT pin.

The circuit is powered by a 3.3 V AVDD power supply. The circuit's master clock is generated by the ADAV801/ADAV803 or an external oscillator, depending on whether the ADAU1761 is configured as a master or slave device. When the ADAU1761 is used as a slave, that is, when BLCK and LRCLK are driven by the ADAV801/ADAV803, MCLK is 256 times the audio clock recovered from the S/PDIF stream. It can also be configured equal to 512 times the recovered clock. This clock is accessed through the SYSCLK3 pin of the ADAV801/ADAV803 and connected to the MCLK pin of the ADAU1761.

When ADAU1761 is the master device, MCLK is generated by the on-chip oscillator and provided to ADAV801/ADAV803 through the MCLKI pin. In this case, the ADAU1761 drives the LRCLK and BCLK lines, and the SRC on the ADAV801/ADAV803 is used to synchronize the audio between the I ^{2 S port and the S/PDIF port.}

Register settings

See www.analog.com/CN0219-DesignSupport for the complete design support documentation package for this circuit note , which includes register set files for the ADAV801/ADAV803 and ADAU1761 in both master and slave configurations. These register setting files can be loaded using the relevant evaluation board software.