Location:Training / Embedded Development / FPGA / How to use Vivado HLS to accelerate FPGA algorithm development / Describing an efficient C testbench - output monitoring and format control

This series of teaching videos will lead you from scratch to master Vivado HLS and UltraFAST design methods from scratch, step by step, helping you become a master of system design and algorithm acceleration! This course includes five topics: the design process of Vivado HLS, coding style when describing algorithms in C or C++, optimization methods of for loops, optimization methods of arrays, and implementation of input/output ports.