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Location:Training / Embedded Development / FPGA / How to use Vivado HLS to accelerate FPGA algorithm development / Array Optimization - Array Splitting

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Array Optimization - Array Splitting
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Duration：13 minutes and 31 seconds
Date：2019/03/20

Uploader：抛砖引玉

Introduction

keywords： FPGA Xilinx living algorithm

This series of teaching videos will lead you from scratch to master Vivado HLS and UltraFAST design methods from scratch, step by step, helping you become a master of system design and algorithm acceleration! This course includes five topics: the design process of Vivado HLS, coding style when describing algorithms in C or C++, optimization methods of for loops, optimization methods of arrays, and implementation of input/output ports.

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