Location:Training / Computer and Programming / Verilog HDL hardware description language advanced training / Static Random Access Memory (SRAM)

The composition of digital systems in FPGA and key points of combinatorial logic design
Key points of sequential logic design
Types and uses of modules
Why Verilog can support
Verilog modules for large-scale design of RAM and stimulus sources How to call RAM top-level test Verilog modules
in Quartus II Composition and combination of digital logic circuits Logic example (1):: 8-bit data path controller Combinational logic example (2): An 8-bit three-state data path controller Switch logic application examples and delay issues Why should static random access memory (SRAM) design a finite state machine (1 ) Finite state machine representation method Global clock king and balanced tree structure Avoid risky competition and pipeline Example 1: Use gate-level structure to describe D flip-flop; Example 2: Write test module to check whether the design is correct through simulation; Example 3: Designed by modules to form a higher-level module; Example 4: D flip-flop with asynchronous reset terminal. Example: Implementation and testing of T flip-flops and counters Example: Design of a 4-bit full adder and instruction decoding circuit using a one-bit full adder Example: Testing of the instruction decoding circuit HDL models at different abstraction levels in FPGA design: System Level, algorithm level, register transfer level, gate level, switch level Key points of sequential logic design Top-level testing Verilog module in FPGA design