Currently, there is a project based on FPGA+DSP architecture. The communication interface in the middle is SRIO. After FPGA processes the data, it sends it to DSP. How does DSP know that the data has
[i=s]This post was last edited by Gong Gong on 2014-10-24 17:37[/i] This article is transferred from the Analog Devices Technical Support Center [url=https://ezchina.analog.com/message/20771#20771]htt
I recently used W77E58 and used a watchdog reset. It worked normally before, but I made some program modifications in other places not related to the watchdog. After that, the watchdog did not work pr
Abstract: Starting from the spatial geometric relationship of spaceborne synthetic aperture radar (SAR), this paper establishes the expression . Taking into account the rotation and oblateness of the
Editor's note: When Wu Jun talked to me about writing this "Top of the Wave" series, I was surprised and moved. I was surprised because in my impression, Wu Jun is a researcher at Google, the author o
I encountered some problems when using uC/OSII: When compiling with ICC AVR Professional Edition 6.31, the following information appeared: C:\icc\bin\imakew -f MainController.mak iccavr -o MainControl