The 2nm chip "war" begins: TSMC's new fin structure solution promotes miniaturization

Modern technology has made remarkable achievements in the design of integrated circuit materials, and has gradually developed several generations of integrated circuits. Each generation has a smaller and more complex structure than the previous generation, which reduces the size while increasing the functional density of the chip.

This miniaturization process is generally aimed at increasing production efficiency and reducing related costs, but it also makes the integrated circuit structure more complex. Because when the chip size continues to shrink, the chip performance and transistor energy efficiency management will become more difficult to control.

In the prior art, a fin field effect transistor device is usually used to improve the performance of a chip, because in this transistor device, the gate surrounds the three sides of the channel, and a dummy gate is usually formed above the parallel fin structure, and then a sidewall spacer is formed on the sidewall of the gate. After the sidewall spacer is formed, the source and drain regions are formed on the fin structure on both sides of the gate. Among them, the dummy gate can be replaced by a real gate, for example, using a conductive material such as a metal material.

However, when the pitch size of the node becomes smaller and smaller, the space of the virtual gate between multiple fin structures becomes smaller and smaller, which may cause damage to the fin structure during heavy etching, thereby limiting the miniaturization development of the pitch and size of the fin structure.

Therefore, TSMC applied for an invention patent titled "Structure of integrated circuit device and manufacturing method thereof" (application number: 202110274387.X) on March 15, 2021, and the applicant was Taiwan Semiconductor Manufacturing Co., Ltd.

Based on the relevant information currently disclosed in the patent, let us take a look at this solution.

As shown in the figure above, it is a schematic diagram of the structure of a fin field effect transistor with improved pitch miniaturization. A group of fin structures 104 are formed on a substrate 102. It can be seen that the space 103 separates many fin structures into different clusters 101. In this scheme, the pitch of these fin structures is less than 24 nanometers, the spatial distance between the fin structures ranges from about 5 to 10 nanometers, and the height is 50 to 60 nanometers. Therefore, compared with ordinary fins, the height of these fins appears to be very large, and taller fins also help improve device performance.

The structures of these fins are all elongated fin-like structures, and their directions are parallel to each other. From the above figure, we can also see the direction of the fin structure from the perspective of the vertical section. In addition, the semiconductor substrate of this scheme uses a silicon substrate, which is also a part of the silicon wafer. Structurally, it is a material with a single film layer of uniform composition. On the fin structure, a hard mask layer 106 and a photoresist layer are also formed. The photoresist is exposed to the light source through the mask and then developed to retain the required part.

There is a large area of ​​blank space between each set of fins. This part is the isolation structure of the FinFET. This part of the structure is a dielectric material, which is used to electrically isolate each set of fins. After depositing the shallow trench isolation material, chemical mechanical polishing is further applied to make the top surface of the workpiece flat and expose the hard mask layer.

As shown in the figure above, a fin field effect transistor device is displayed along the gate spacer. The sidewall spacer of the gate is composed of an upper spacer 124 and a lower spacer 126, which are located at the upper and lower parts of the gate, respectively. The top of the lower spacer is adjacent to the top surface of the fin structure, and the top surfaces of the two are in the same plane. Therefore, the bottom surface of the upper spacer is also in the same plane as the top surface of the fin structure. In addition, in the space between multiple fin clusters, the bottom of the upper spacer directly contacts part of the second dielectric layer 116 and the first dielectric layer 112, thereby forming a dielectric stack.

As shown in the above figure, which is a structural schematic diagram of a fin field effect transistor device, it can be seen that the gate device 134 includes a sidewall spacer, which has an upper spacer and a lower spacer, and both the upper sidewall spacer and the lower sidewall spacer isolate the gate device from the source and drain regions 128.

Finally, we can see that the figure above is a flow chart of the preparation method of this fin field effect transistor structure with improved pitch miniaturization. First, a first set of fins is formed on the substrate. The structure of the fins can be processed by a patterning process and formed by photolithography. And a sacrificial material is set between multiple fin structures. The sacrificial material can be selected from silicon nitride or silicon germanium, which are easier to fit into the space between multiple fin structures.

Secondly, a dummy gate is set above the fin structure and the sacrificial material, and a sidewall structure is formed thereon. The sacrificial material is laterally etched to leave a hole under the sidewall spacer. The thickness of the hole is greater than the sidewall structure, about 5 to 15 nanometers. Finally, the dummy gate is removed and a real gate is formed above the fin structure, thereby obtaining a higher structure fin structure and a more miniaturized structure.

The above is the integrated circuit device solution invented by TSMC to achieve chip miniaturization by improving the fin structure. This solution achieves a higher-sized fin structure through a new fin structure and the use of dielectric stacking. It is not only beneficial to improve chip performance, but also conducive to chip miniaturization.