Samsung successfully taped out 3nm GAA chip

According to Jiwei.com, Samsung recently announced that the 3nm process technology using GAA architecture developed in cooperation with Synopsys has officially been taped out.

At the 3nm node, Samsung was more aggressive and directly chose the next-generation process technology - GAA surround gate transistor. By using nanosheet devices, it manufactured MBCFET (Multi-Bridge-Channel FET), which can significantly enhance transistor performance and mainly replace FinFET transistor technology.

The process requires a different set of design and certification tools than the FinFET transistor structure, so Samsung used Synopsys' Fusion Design Platform. The physical design kit (PDK) for the process was released in May 2019 and was certified last year. Samsung's 3nm GAA process is expected to be used in high-performance computing (HPC), 5G, communications, AI and other fields.

In terms of technical performance, GAA transistors can provide better electrostatic characteristics than FinFETs and can meet certain gate width requirements. This is mainly reflected in the fact that under the same size structure, GAA's channel control ability is enhanced, thereby providing the possibility of further miniaturization.

According to Samsung, the 3nm GAA technology improves logic area efficiency by more than 35%, reduces power consumption by 50%, and improves performance by about 30% compared to the 5nm manufacturing process.

"Samsung Foundry is central to driving the next phase of industry innovation as we continually evolve process-based technologies to meet the growing demands of specialized and broad market applications," said Sangyun Kim, vice president of Samsung Foundry Design Technology Team. "Our latest, advanced 3nm GAA process benefits from our extensive collaboration with Synopsys, and the promise of the Fusion Design Platform to accelerate preparations for efficient 3nm process implementation is a testament to the importance and benefits of these key alliances."

"The GAA transistor structure marks a critical inflection point in process technology advancement, which is critical to maintaining the scaling trajectory required for the next wave of hyperscale innovation," said Shankar Krishnamoorthy, general manager of the Digital Design Group at Synopsys. "Our strategic collaboration with Samsung Foundry supports the joint delivery of best-in-class technologies and solutions to ensure the continuation of these scaling trends and the associated opportunities these provide for the broader semiconductor industry."

The 3nm GAA process tape-out means that the process is one step closer to large-scale application, but the final progress is still unclear. Samsung first said that it would be mass-produced in 2021, but later postponed it to 2022, and TSMC's 3nm process will be mass-produced next year. For TSMC, Gate-all-around FETs (GAAFET) are also part of its development roadmap. The company is expected to use a new transistor architecture in its "post-N3" technology (possibly N2).