TSMC's 2nm process has made a major breakthrough, and the yield rate of risk trial production will reach 90% in 2023

TSMC has made a major breakthrough in its 2nm process, and its R&D progress is ahead of schedule. The industry is optimistic that its risk trial production yield will reach 90% in the second half of 2023. The supply chain revealed that unlike 3nm and 5nm using fin field-effect transistors (FinFET), TSMC's 2nm process uses a new multi-bridge channel field-effect transistor (MBCFET) architecture.

It is reported that TSMC established a 2nm project R&D team last year to find a feasible path for development. Considering multiple conditions such as cost, equipment compatibility, technology maturity and performance, 2nm adopts the MBCFET architecture based on the gate-all-around (GAA) process to solve the physical limit problem of current control leakage caused by FinFET process miniaturization.

The improvement of extreme ultraviolet (EUV) micro-development technology has made TSMC's key nanosheet stacking technology, which has been developed for many years, more mature, and the yield improvement progress is smoother than expected. TSMC previously revealed that 2nm R&D and production will be in Baoshan, Hsinchu, and four super-large wafer factories from P1 to P4 are planned, covering an area of ​​more than 90 hectares.

Image source: Taiwan Economic Daily

Judging from TSMC's current 2nm R&D progress, the supply chain expects TSMC to enter risk trial production in the second half of 2023 and formal mass production in 2024. In April this year, there were also reports that TSMC was already researching the 2024 2nm iPhone processor and had begun researching nodes below 2nm.

Transistors are the key to breakthroughs in advanced semiconductor processes. For example, at the 45nm stage, the industry introduced the high-k dielectric/metal gate (HKMG) process, and at 32nm, the second-generation high-k dielectric/metal gate process was introduced. However, when the transistor size is less than 25nm, the size of traditional planar field-effect transistors can no longer be reduced.

The Fin Field-Effect Transistor (Fin Field-Effect Transistor) invented by Professor Hu Zhengming of the University of California, Berkeley, solved this problem. The main idea is to make the field effect transistor three-dimensional. This new complementary metal oxide semiconductor transistor can improve circuit control, reduce leakage current, and shorten the gate length of the transistor.

Thanks to the invention of FinFET, Intel launched the commercialized 22nm FinFET in 2011. Since then, based on FinFET, the industry has pushed the semiconductor process from 22nm to the current 5nm. However, the 5nm process has shrunk the transistor to the atomic level. The diameter of a silicon atom is 0.117nm, and 3nm is about the length of 25 silicon atoms connected end to end.

To continue to miniaturize semiconductor processes, new technologies need to be introduced. TSMC's 2nm uses GAA (Gate-all-around), or GAAFET, which has the same concept as FinFETs, but the difference is that the gate of GAA wraps around the four sides of the channel, and the source and drain no longer contact the substrate.

Depending on the design, GAA also has different forms. Currently, the four mainstream technologies are nanowires, plate-like multi-path bridge fins, hexagonal cross-section nanowires, and nanorings.

The GAA technology introduced by Samsung is Multi-Bridge Channel FET (MBCFET), which is a plate-like structure with multiple bridge fins.

TSMC also uses the MBCFET architecture. TSMC President Wei Zhejia recently revealed at a dinner of the E.Shan Technology Association that with each generation of TSMC's process advancement, the speed and performance of customers' products can be improved by 30%-40%, and power consumption can be reduced by 20%-30%.

Samsung is more aggressive in adopting GAA technology. It is reported that Samsung will introduce GAA at 3nm, which will improve the performance of its 3nm process by 35% and reduce power consumption by 50% compared with 7nm. However, TSMC will not introduce GAA technology until 2nm.

Image source: IBS

GAA can reduce performance and power consumption, but the cost is also very high. Data from market research firm International Business Strategies (IBS) shows that the cost of chips rises rapidly after 28nm. The cost of 28nm process is $62.9 million, and 5nm will soar to $476 million. Samsung said that the cost of its 3nm GAA may exceed $500 million.

New transistors may also bring revolutionary changes. A transistor architecture called Bizen may break the limits of CMOS from another direction.