Application of TMS320C542 in offline video encoding/decoding system

　　On the one hand, the purpose of video image encoding/decoding is to convert analog video signals into digital signals for transmission. On the other hand, since the amount of image data obtained by simple video analog-to-digital conversion is very large, image compression technology must be applied to reduce the data. quantity. There are two implementation methods in the field of image encoding/decoding. One is based on a microcomputer platform. The image data is compressed and encoded through microcomputer software or an image processing card based on a microcomputer bus, and can be processed through a PC network. data transmission. Another method abandons the microcomputer platform and uses DSP-based microprocessor algorithms to compress/decompress images and encode/decode them. The system composed of the latter method is called an offline image system. Offline imaging systems have received widespread attention due to their small size and flexible and easy application. With the development of microprocessing technology, dedicated image compression/decompression ASIC chips have emerged, and image processing algorithms have been integrated into ASICs, which simplifies the design and implementation of offline image systems.

　　Although the dedicated image compression/decompression chip has integrated encoding/decoding algorithms, real-time adjustment of the image compression effect, data rate control and image data transmission still require high-speed microprocessor control and implementation. This article mainly introduces the design and application of high-speed DSP chip TMS320C542 in an offline video image encoding/decoding system from the perspective of hardware design.

　　1 Peripheral interface function of TMS320C542

　　 TMS320C542 is one of the C54x series DSPs of American TI Company. It is a high-speed microprocessor chip with 16-bit fixed-point operation. The operation speed is 40MIPS, the operating voltage is 5V, and the on-chip RAM has 10K words. It is the largest on-chip RAM in this series. The main peripheral hardware interface functions of C542 are as follows:

·Parallel IO interface, including 16-bit address line and 16-bit data line. The address line is a unidirectional output pin, and the data line is a bidirectional pin. The interface also works with the data area strobe signal DS, the program area strobe signal PS, the IO port strobe signal IS, the data latch signal MSTRB for storage access, the data latch signal IOSTB for IO port access, and the read and write signals. R/W.

·5 external interrupt signal lines, one of which is a non-maskable interrupt and the remaining 4 are maskable interrupts.

·1 program condition jump control input line and 1 external flag signal output line XF.

·Two serial communication signals, one of which is a high-speed serial port BSP with data buffer, and the other is a time division multiplexing TDM serial communication port. The data buffer serial port BSP is composed of a full-duplex serial interface and a data buffer that can reach a maximum length of 2K words. When the buffered send/receive mode is used, the sending/receiving process of data in the buffer does not affect the DSP running other programs. code.

·The main control interface HPI is used for data access control between the external processor or microcomputer bus and the DSP. An external processor or microcomputer can use this interface to access the designated memory space inside the DSP to read or write data without hindering the normal operation and processing of the DSP's internal program. Even if the external processor is slow, the HPI interface will not slow down or stop the DSP's operations. If the external processor needs to apply for DSP services, this port can also be used to trigger the corresponding interrupt of the DSP.

　　As the core of the offline video encoding/decoding system, DSP not only needs high-speed computing capabilities, but also hopes to provide good peripheral interfaces and communication interfaces. The performance of C542 meets the needs of this system.

　　2. Peripheral relationship of DSP.

　　 There are many peripheral devices of DSP in this system, and each has its own special function and usage. Therefore, straightening out their electrical relationship is the primary issue in system design.

　　2.1 The peripheral C542 running program required for DSP program loading

　　requires an external device to help the DSP store the program, except that the manufacturer directly burns it into the on-chip ROM. After the system is powered on and reset, the program code must first be loaded from the chip into the DSP's on-chip RAM before execution. C54x provides a variety of program loading methods: HPI interface program loading method, 8-bit I/O interface program loading method, 16-bit I/O interface program loading method, 8-bit parallel EPROM program loading method, 16-bit parallel EPROM program loading method method and serial port program loading method. This system chooses to use a 32K×8bit EPROM to load the program to the DSP using the 8-bit parallel ERTPM program loading method.

　　After the DSP is powered on and the telegram bit is set, it first reads the data SRC with the IO port address OFFFFh. The lowest two bits 1-0 of this 16-bit data SRC determine the program download method selected by the user. When these two bits are 01, the 8-bit parallel EPROM program loading method can be selected. Then, the result of multiplying bit7-2 bit data of SRC by 2 10 will be used as the starting address for DSP to access EPROM. Thereafter, the DSP will load the program code from the data area starting from this starting address into the program area for execution.

　　This system uses a 32K×8bit EPROM as a data space with a starting address of 8000h to store and load the program. At this time, bit7~0 of SRC should be set to 10000001. According to the CMOS circuit specification, this system uses a 4.7kΩ resistor to pull up bits 0 and 7 of the DSP data line to high level, while bits 1 to 6 of the data line use a 4.7kΩ resistor to pull down to ground. The use of resistors will not affect the correct logic on the data line when a device drives the data bus. On the other hand, when the DSP accesses the IO port of 0FFFFh, as long as other chips release the data bus, the DSP can read the correct SRC data.

　　2.2 Dedicated video image encoding/decoding ASIC

　　Dedicated video image encoding/decoding ASIC can provide a 16-bit data interface, and select the data to access different internal registers of the ASIC through 4 address lines. Through this interface, DSP can set the working status of video image encoding/decoding and the image compression effect. Through this interface, DSP can also read relevant statistical data of the image, such as the total brightness of the image, the maximum brightness and minimum brightness of the pixels, etc., in order to provide a basis for the DSP to adjust the compression effect. Through this interface, compressed image data can also be read or written. At this time, the interface is equivalent to a FIFO interface. This dedicated video encoding/decoding ASIC can actively issue a service request interrupt and request data from the DSP. Access and control processing.

　　According to the interface characteristics of this dedicated video encoding/decoding ASIC, this system uses the IO port of the DSP to access and process the peripheral device.

　　2.3 Low-speed control microcontroller

　　DSP, as a high-speed computing processor, is not suitable for low-speed control applications. In this system, the adjustment of image brightness, color and contrast, the control of camera pan/tilt, the reception of user controller signals and the display of system working status indicators are all low-speed controls. This system uses a single-chip microcomputer to complete these tasks, which also requires DSP and single-chip microcomputer to exchange control commands.

　　The HPI interface of C542 provides a good solution for communication between DSP and microcontroller. Although the 8 data lines and 5 access control lines of the HPI interface occupy 13 IO pins of the microcontroller, all the microcontroller IO resources of this system are sufficient. With the HPI interface, the microcontroller can send user commands to the DSP and apply for DSP processing by triggering a DSP interrupt. The DSP can also request the microcontroller to perform corresponding operations through the HPI interface. Taking advantage of the characteristics of the HPI interface, the communication between the two microprocessors does not have to match the data input rate, nor will it affect the execution speed of their respective programs.

　　2.4 Image data storage SRAM

　　requires memory to buffer data in order to achieve flow rate control of data transmission. At the same time, sufficient storage space is also required to implement image freezing and other processing functions. This system chooses 128K×16bit high-speed SRAM to expand the limited storage space of C542. The internal RAM of C542 occupies the data area with addresses from 0000 to 27FFh. The data area from 8000 to 0FFFFh has been allocated to EPROM to place program code. Finally, only the addresses from 2800 to 7FFFh can be used by SRAM. One way to extend the SRAM access address line is to use the twice addressing method. For the first time, part of the address is given and cached, and the data is not accessed at this time; during the second access, the remaining address data is given, and then the spliced ​​total address is used to access the data.

　　Since image data is a data stream, its storage and reading in SRAM are in increasing address order. Based on this characteristic, this system designs a new SRAM address line expansion method. This method divides every 32 16-bit word image data into the smallest unit group of one data operation. The upper 12 bits of the address stored in the SRAM for these 32 words of data are the same. The upper 12 bits of the address are selected by the lower 12 bit address lines of the DSP. The lower 5-bit address of SRAM is automatically generated by a 5-bit binary counter. That is, every time the upper 12-bit address is accessed, the lower address is automatically incremented by 1. In this way, only the 12 address lines of the DSP are actually used, and the access can be efficiently performed. All storage space of SRAM. Finally, the high four bits A15~12 of the DSP address line should select two values ​​between 0011~0111, one is used to chip select SRAM, and the other is used to reset the counter.

　　2.5 Data communication high-speed serial port

　　This system directly uses the buffered serial port BSP of C542 as the communication interface that the system opens to users. The data rate of this interface can reach up to 40Mbps, and the length of the data packet can be selected from 8 bits, 10 bits, 12 bits and 16 bits. The receiving part BSPR of the BSP serial port works in passive mode, and the clock and frame synchronization signals accompanying the received data should be provided externally. The sending part of the BSP serial port, BSPX, can work in active mode, and its data clock and frame synchronization are provided internally by the DSP. BSPX can also work in passive mode, with the data clock and frame synchronization clock input from the outside. BSP's buffer data automatic sending and receiving function also simplifies DSP processing work. This system adds an interface driver based on the BSP serial port of the DSP, which constitutes the communication interface of the system.

　　3. System design of the DSP part.

　　 Figure 1 is the schematic diagram of the core DSP part of this offline video encoding/decoding system. The buffer serial port of the DSP alone constitutes the user communication serial port. The HPI interface of the DSP implements the DSP and low-speed control microcontroller. communication between. The remaining peripherals connected to the IO interface of the DSP are power-on reset SRC data logic, program loading EPROM, video image encoding/decoding ASIC and image data storage SRAM. EPROM and SRAM are processed as DSP extended data storage areas, and SRC data logic and video encoding/decoding ASIC are accessed as DSP IO ports. From the perspective of program instructions, the access operation of the data storage area should use the data access instructions of the DSP, such as LD, ST, MVDD, etc., while the access of the IO port should use the IO port access instructions PORTR and PORTW of the DSP.

　　The 16-bit data lines and 16-bit address lines of the DSP's IO interface constitute the data bus and address bus of the peripheral device. Small-scale MACH programmable logic devices are used to design access control logic for IO peripheral devices. The chip select and read and write signals of each device generated by MACH are determined by its relationship with the DSP, its addressing range, and pin signal characteristics. For example, the program download EPROM is a DSP extended data area with an addressing range of 8000~0FFFFh. If its chip select signal is active high, the EPROM chip select logic is:

CS-EPROM=(!DS)&A15

　　When the DSP accesses the data area, DS is valid and is low level, and when the highest bit A15 of the address line is 1, the CS_EPROM signal is valid and the EPROM is gated. In addition, the binary five-bit counter for automatic increment of SRAM access address is also implemented by MACH programmable logic device, constructing additional 5 address lines.

　　By utilizing the DSP and HPI interface functions of the DSP chip TMS320C542 and combining it with the MACH programmable logic chip to expand the IO interface function of the DSP, the offline video chip can be expanded to the IO interface function of the DSP, thus the offline logic chip expansion can be realized. The IO interface function of DSP realizes the design of the control core of the offline video image encoding/decoding system. Through actual debugging, the DSP can correctly download the program code from the EPROM and run it during power-on reset. The DSP can correctly access the video encoding/decoding ASIC and data storage SRAM. The command data exchange between the DSP and the microcontroller and the transmission of serial port data are all correct. can be implemented normally. This hardware design with reasonable structure and compact layout provides convenience for further software development. The instruction code for DSP access to peripheral data, especially the access operation to SRAM, is simple and efficient, which saves valuable instruction cycle resources for other image real-time control algorithms in the DSP program software.