Application of VRS51L3074 and Serial FRAM in LED Display Screen

VRS51L3074 is a single-cycle 8051 microprocessor produced by Ramtron that can run at a speed of up to 40MIPS. The memory subsystem of VRS51L3074 has 64 KB Flash, 4,352 bytes of internal SRAM, and numerous peripheral interfaces. The high-speed enhanced SPI interface of VRS51L3074 has a speed of 1/2 of the system clock, and has the functions of multi-byte transmission, manual chip selection, and output download pulse. These functions are essential for directly using the SPI interface to read the display data in the serial Flash and transmit it to the LED display screen at the same time. FRAM technology is a storage device developed by Ramtron that combines the characteristics of RAM and ROM and has the read and write speed of RAM and can be retained after power failure. FRAM series storage chips have many advantages such as no delay in writing data, strong anti-interference ability, no limit on the number of FRAM read and write times in a 3.3V environment, and data retention time of up to 10 to 45 years. FRAM products provide a variety of interfaces (such as I2C, SPI, parallel interface), multiple capacities (4Kb, 16 Kb, 64 Kb, 256 Kb, 1 Mb, etc.), and multiple voltage levels. FM25L256B is a 32K×8-bit FRAM with an SPI interface. Since the SPI bus is a four-wire system, when the FRAM with an SPI interface forms a dual-port RAM, the switching of the data line and the control line is very convenient, so using FRAM becomes the best choice for forming a large-capacity dual-port RAM.

1. Requirements of LED display control system for serial FRAM

First, the connection relationship between the data processing system composed of three FRAMs controlled by VRS51L3074 and FRAM is analyzed. Figure 1(a) shows the data processing system composed of VRS51L3074 and three FRAMs. When displaying data, the SPI bus is in the standard connection form, that is, the SI, SO, and SCK of all SPI interface chips are connected together; only the chip select line is connected to VRS51L3074 respectively, and the data of each memory is read and written respectively. When displaying data, it is only necessary to synchronously give the same starting address to the three serial memories, and then send it to 74HCl64 from the SO pin of the serial FRAM memory under the action of the SCK pulse, and then directly output it to the LED display after serial-to-parallel conversion. Since the display data is directly bypassed by 74HCl64 "DMA" to the LED display, the VRS51L3074 as the data display control does not need to process the output data of the serial memory, that is, only open-loop control is required for the three serial memories. The specific circuit block diagram is shown in Figure 1(b).

2. Dual-port RAM module and LED display control system

The serial dual-port RAM module shown in Figure 2 is constructed based on the connection relationship between the data processing and data display SPI in Figure 1, plus a bus switch 74HC245. The FRAM clock signal SCK and the data input terminal SI of the SPI interface are shared, and because the three chip select signals must be valid at the same time when driving the LED display, the data output SO terminal (as shown in Figure 1 (b) and connected to the input terminals of three 74HCl64s) also needs to be independently controlled, so the control signals that need to be switched between ports A and B by the 74HC245 bus switch are 8 (SI, 1; SCK, 1; CS, 3; SO, 3), and it is sufficient to use two 8-bus data switches 74HC245.

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Figure 3 shows an LED display control system composed of two serial dual-port RAM modules. During operation, the data processing microcontroller and the data display microcontroller work synchronously through two control lines, in which the data processing microcontroller is the host and the data display microcontroller is the slave. In practical applications, the height of the LED display can be increased by increasing the number of serial dual-port RAM modules or increasing the number of 74HCl64 levels. The horizontal length of the LED display is only related to the SPI clock frequency of the data display microcontroller and the serial FRAM. When the SPI clock frequency is 20 MHz, the horizontal length can reach 2 048 dots. In the bidirectional driving mode, the height of the LED display is determined by the number of serial dual-port RAM modules. The horizontal length can reach 4 096 dots without grayscale at 40 MHz and 512 dots under 8 grayscale levels; and the vertical length of the three FRAMs after 74HCl64 serial-to-parallel conversion is 3 bytes (24 bits in total), the number of two-color dots = 24÷2x16=192 dots, and the number of single-color dots = 24×16=384 dots.

The reading and writing of FM25L256B serial FRAM is basically the same as that of serial Flash. The biggest feature is that after writing a byte, there is no need to check whether the write operation is completed like serial Flash, but to write continuously like a sequential read operation; there is no need to erase before writing, and there is no limit on the number of reads and writes, so it can be used completely like RAM. The SPI interface speed of VRS51L3074 is 1/2 of the system clock. The SPI interface speed of general 51 microcontrollers is 1/4 of the system clock (without download pulses). Therefore, some characteristics of the SPI interface of VRS51L3074 play an extremely important role in the LED display control system. Similarly, the dual-port RAM control system composed of serial FRAM and VRS51L3074 can use the SPI interface of VRS51L3074 to easily complete multi-byte reading and writing.

3. Dual MCUs share dual-port RAM to work together

First, the data processing microcontroller organizes the same display data in module O and module 1, and then starts the data display microcontroller through the display control terminal. The data display microcontroller has only the power to read the serial FRAM, and can only select the three FRAMs in module 0 or 1 through the CSO chip at the same time, and send the first address of the display data to the three FRAMs in module O or 1 through the SO terminal at the same time; then under the action of SCK, the three FRAMs in module O or 1 output the display data to the corresponding SI terminal of 74HCl64 through their respective SO terminals, and the data display microcontroller automatically generates the shift pulse required by the LED display unit board through the CS3 terminal. After the LED display screen completes the display of a row, the data display microcontroller sends a status signal of the row display completion to the data processing microcontroller, and waits for the data display microcontroller to send a command to continue display, and starts the display of the next row after receiving the command to continue display. The data processing microcontroller can select the data display microcontroller to display the display data in module O or 1 through the port as needed, and the microcontroller can process the display data in the dual-port RAM module 1 or 0 while the data display microcontroller displays.

Conclusion

This paper makes a preliminary discussion on the hardware system and control method of the LED display control system using a dual-port RAM composed of serial FRAM memory. The difference between this dual-port RAM and the traditional dual-port RAM is that one end of its port can read and write, while the other end can only read. The dual-port RAM composed of serial FRAM has the advantages of fewer control lines, large capacity and low price, and has a good application prospect when the read and write speed requirements are not very high.