Design of AT056TN04 LCD screen driver controller

Abstract: As the resolution is larger than that of analog screens, the lines on the glass will be denser, and the cost of process and backlight is higher. In the field of industrial instruments and meters that do not require high color, low-cost analog color LCD screens have become the first choice. A design scheme of color LCD driver controller based on FPGA technology is proposed. The hardware description language is used to complete the LCD timing and memory interface, and the 8 basic colors of AT056TN04 are successfully displayed. It not only overcomes the shortcomings of monotonous color of monochrome LCD modules and high price of colorful digital color screens, but also has the advantages of small display data volume and simple and convenient user operation. Appropriate adjustment can be conveniently applied to other analog color LCD screens, and has good application value in industrial instruments and meters.

In order to make the product in a strong position in the market competition, it is an inevitable trend that monochrome LCD screens are gradually replaced by color screens in industrial instruments. Due to the high resolution of digital color screens, the lines on the glass will be denser, and the process and backlight costs will be higher than analog screens. Therefore, in the field of industrial instruments with low color requirements, low-cost analog screens have become the first choice. This design is aimed at the AT056TN04 TFT analog LCD screen of Innolux, which has a good application background in industrial instruments, and uses FPGA technology to realize its drive controller design.

1 Display memory arrangement

The LCD control drive timing controller sends the data in the display memory to the LCD screen in a cycle under the control of the system clock, the line synchronization clock and the frame synchronization clock, and completes the update of the display memory data under the control of the microprocessor. To simplify the design, each color of the LCD screen pixel is quantized by 1 b, which can realize 8 basic colors, and the circuit is simple to implement. To facilitate the structural arrangement, the coordinates of the first point in the upper left corner of the LCD screen are (0, 0), and the coordinates of the lower right corner are (233, 319). 64 KB SRAM is selected as the display memory, and each storage unit represents a color component of 8 adjacent pixels on the LCD screen, where red is stored in the unit with the tail address of 00, green is 01, and blue is 10. Although the unit with the tail address of 11 is wasted, addressing is very convenient. The upper 8 bits of the 16-bit address line are the row address, the middle 6 bits are the column address, and the lower two bits are the color address.

2 LCD drive timing design

The most important interface signals in the AT056TN04 drive signal are: frame start pulse STV, scan drive shift clock CKV, scan drive output enable control OEV, common electrode drive signal Vcom, data drive output enable control OEH, row scan start pulse STH, data sampling and shift clock CPH. The display process of AT056TN04 is as follows: First, the frame start signal STV starts the display of a frame of data. After a period of time, OEV changes from low to high and maintains tOEV, then changes from high to low. At the same time, VCOM jumps, OEH changes from high to low and maintains tOEH, then changes from low to high. After tDIS1, STH changes from low to high, maintains tSTH, and then changes from high to low, thereby starting the display of the first line. During this period, CKV changes from low to high and maintains tCKV, then changes from high to low. After a line of display is completed, the next line of display is changed, and this is repeated. After a frame of data is displayed, this process is continuously repeated. The timing details are shown in Figure 1.

All time intervals in the figure are integer multiples of CPH, so the counter tcph is used to count CPH, and judging the value of tcph can generate other control signals, while ensuring the synchronization of various signals. The time requirements of each interface signal have been given in the manual of AT056TN04. CPH is the smallest unit in the entire timing, with a period of 154 ns and an error of no more than 4 ns. A 13 MHz active crystal oscillator is used, with a clock period of 76.9 ns. It is divided by 2 to obtain a CPH clock of 153.8 ns. Each frame of data of AT056TN04 contains 256 to 268 lines, and the actual number of display lines is 234 lines, of which the last few lines do not display data. The external controller can read and write the display memory in these lines that do not display data. In this design, the number of rows per frame of data is set to 260, so STV will generate a pulse every 260 rows. A row counter th is used. When tcpvh is 260 (i.e. one row is displayed), th is increased by 1 to generate STV. After STV appears, it needs to be delayed by tSV (3 rows). The time for each row is designed to be 800 CPH, and the counting state of tcpvh is shown in Figure 2.

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3 LCD screen refresh module design

AT056TN04 is configured to scan from left to right and from top to bottom. Each time, the three-color information (3 B) of 8 points is read and stored. Under each CPH clock, the three-byte RGB data is simultaneously shifted to the left by one position. The RGB output pin of PFGA is connected to a 4.7 kΩ pull-up resistor to a 5 V power supply to generate VR, VG, and VB signals to drive the LCD screen. Under the action of the RAM read-write control module and the timing module, the controller will display the image data in the RAM and send it to the LCD screen for display. Using the counters th and tcpvh, it is convenient to generate addresses, thereby realizing the read and write operations of the RAM. The th value is used as the row address, tcph[9:4] is used as the column address, and tcph[1:O] is used as the color address.

The simulation results in QuartusⅡ are shown in Figure 3 and Figure 4, where Figure 3 is the waveform of each signal when the line is changed, and Figure 4 is the waveform of each signal when the frame is changed. It can be seen from the results that the waveform fully meets the design requirements.

4 Conclusion

Based on the reasonable memory arrangement and row and column counter design, the LCD timing control and display memory data reading and writing are cleverly completed to realize the display control of 8 basic colors of AT056TN04. Due to the use of FPGA design, it can be applied to other LCD modules in the form of soft core with a little modification, overcoming the shortcomings of monochrome LCD modules with monotonous colors and high prices for colorful digital color screens. It has certain application value in industrial instruments that do not require high colors.