Renesas Releases Next-Generation Dynamically Reconfigurable Artificial Intelligence Processor (DRP-AI) Accelerator

Publisher:悦耳旋律Latest update time:2024-03-08 Source: 瑞萨嵌入式小百科Author: Lemontree Reading articles on mobile phones Scan QR code
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Recent vision models have to handle dynamic and complex environments, thus requiring higher energy efficiency and speed in real-time applications.

In order to meet market demand, the next-generation dynamically reconfigurable (DRP-AI) accelerator was released. The DRP-AI accelerator provides a high power efficiency of 10 TOPS/W, which is 10 times higher than traditional technology. It can run complex image AI models on low-power traditional processors (MPUs) without the need for high-power consumption as before.

In addition to this AI accelerator, the high-end RZ/V2H MPU is also equipped with an image processing accelerator using a dynamically reconfigurable processor (DRP) , a quad-core Cortex-A55 processor running at up to 1.8GHz, a dual-core 800MHz Arm Cortex-R8 high-speed real-time processor, and an I/O processing Arm Cortex-M33 sub-core, in a heterogeneous multi-processor configuration.

Dynamically Reconfigurable Processor (DRP)

The combination of seven Arm-based cores, next-generation DRP-AI, and DRP can instantly process image recognition and AI judgment results in control, making it an ideal AI processor for next-generation autonomous, self-driving mobile robots, and other applications.

Next-generation AI accelerator DRP-AI

The RZ/V2M, RZ/V2L, and RZ/V2MA embed the Renesas original DRP-AI accelerator, but Renesas has upgraded its original AI accelerator DRP-AI to the next generation to meet recent market needs.

To significantly improve efficiency, DRP-AI applies INT8 quantization and support for unstructured pruning, which is difficult to achieve with traditional AI accelerators, to achieve up to 80 TOPS inference performance and 10 TOPS/W power efficiency.

Next Generation Energy-Efficient AI Accelerator (DRP-AI3): 10X Faster Embedded Processing in Advanced AI for Autonomous Systems" White Paper

Figure 1 below shows the comparison of AI inference performance with other RZ/V. Taking ResNet-50 as an example, the performance of a typical classification convolution (CNN) is 14 times higher than that of RZ/V2L without pruning (dense model), and RZ/V2H with model pruning is 45 times higher than RZ/V2L (dense model).

Figure 1 RZ/V series AI inference performance (excluding pre-/post-processing)

Unlocking CV acceleration through the dynamically reconfigurable processor DRP

Even before the advent of AI, various methods have been used in applications for image recognition and decision making. The open source library OpenCV is one such example. Even with the advent of AI image processing, OpenCV remains a very useful technology. Vision AI and OpenCV are now being used together in appropriate scenarios.

To accelerate various image processing such as AI and OpenCV, the RZ/V2H MPU is designed with a dynamically reconfigurable processor separated from the DRP-AI, providing the DRP library for the OpenCV accelerator to take full advantage of its flexibility.

Figure 2 compares the performance of the OpenCV accelerator with DRP and the RZ/V2H quad-core CPU. For example, by using DRP acceleration, the Sobel for image edges is accelerated from 7.6fps to 123fps, a 16x improvement.

Figure 2 OpenCV accelerator performance benchmark

AI heterogeneous configuration + high-speed real-time control

While fast multi-core Linux processors are the best choice for image AI, they require large memory resources and have difficulty achieving the sub-millisecond real-time performance required for mechanical control.

To address this issue, the RZ/V2H uses a quad-core Cortex-A55 to run Linux programs including AI processing, and a dedicated high-speed real-time processor for processing in applications requiring high real-time performance such as .

By using OpenAMP to connect different operating systems between processors, the results of decisions made by the DRP-AI and Linux processors can be reflected in the real-time machinery control of the RTOS processor.

Figure 3 RZ/V2H block diagram

The RZ/V2H embedded AI with these unique features is now in mass production, and the RZ/V2H evaluation board is also available to jumpstart your next vision AI development.





Review editor: Liu Qing

Reference address:Renesas Releases Next-Generation Dynamically Reconfigurable Artificial Intelligence Processor (DRP-AI) Accelerator

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