A CPLD-based microcontroller and PCI interface design solution

　　0 Preface

　　8-bit microcontrollers are widely used in embedded systems. However, allowing them to directly interact with PCI bus devices has its inherent flaws. The 8-bit microcontroller only has 16-bit address lines and 8-bit data ports. In the PCI bus 2.0 specification, in addition to the 32-bit address data multiplexing AD[3~0], there are also important signal lines such as FRAME, IRDY, and TRDY. It is impossible to directly control so many signal lines with the limited I/O ports of a microcontroller. A feasible solution is to use CPLD as a bridge between the microcontroller and PCI devices, and make full use of the advantages of rich I/O resources and user-customizable logic in CPLD to help the microcontroller complete the communication task with PCI devices.

　　1 PCI interface design principle

　　1.1 Introduction to PCI bus protocol

　　Only the PCI bus 2.0 protocol is discussed here. Other protocols are only some extensions based on 2.0. They are of little significance only in terms of communication between the microcontroller and PCI devices. The PCI bus is a high-performance local bus with an operating frequency of 0~33MHz and can support multiple groups of peripheral devices at the same time. Here, we only care about the communication between the microcontroller and a PCI device, and one side of the microcontroller and CPLD is the master, and the other is the PCI slave device. The purpose of this is to simplify the problem and reduce the system cost.

　　Although there are many signal lines on the PCI bus, not every signal needs to be used. In fact, PCI devices do not support all signal lines. For example, the error reporting signals PERR and SERR are not supported in the network card. We can choose to support some of these signal lines for specific applications, and some signal lines can be directly connected to power or ground. The following is a brief introduction to the functions of commonly used signal lines.

　　AD[31～0]: Address data multiplexing signal. It is the address in the first period when FRAME is valid, and it is data when IRDY and TRDY are valid at the same time.

　　C/BE[3～0]: Bus command and byte enable control signal. What is transmitted in the address is the bus command; in the data period is the byte enable control signal, which indicates which bytes in AD[31~0] are valid data. The following is a description of the bus command encoding:

　　　　C/BE[30]# Command type description C/BE[30]# Command type description

　　　　0 0 0 0 Interrupt Acknowledge 1 0 0 0 Reserved

　　　　0 0 0 1 Special period 1 0 0 1 Reserved

　　　　0 0 1 0 I/O read 1 0 1 0 Configuration read

　　　　0 0 1 1 I/O write 1 0 1 1 Configuration write

　　　　0 1 0 0 Reserved 1 1 0 0 Memory multi-line read

　　　　0 1 0 1 reserved 1 1 0 1 dual address cycle

　　　　0 1 1 0 Memory read 1 1 1 0 Memory row read

　　　　0 1 1 1 Memory write 1 1 1 1 Memory write is invalid

　　　　All data transmission on the PCI bus is basically controlled by the following three signal lines.

　　 FRAME: frame period signal. Driven by the main device, it indicates the start and duration of an access. When FRAME is valid (0 is valid, the same below), it indicates that data transmission is in progress. After it fails, it is the last cycle of data transmission.

　　IRD: The master device is ready for signal. Driven by the master device, it indicates that the master device is ready for data transmission.

　　TRDY: The slave device is ready for signal. Driven by a slave device, indicating that the slave device is ready for data transfer. When IRDY and TRDY are valid at the same time, data transmission will actually occur.

　　In addition, there is an IDSEL signal used as a chip select signal during configuration space reading and writing. For the case where there is only one PCI slave device, it can always be connected high. The IDSEL signal is driven by a slave device, indicating that the device has become the currently accessed slave device and can be ignored.

　　When reading and writing operations are performed on the PCI bus, except for RST, IRQ, IRQC, and IRQ, only the falling edge signal of the clock will change, while the signal on the rising edge of the clock must remain stable.

　　1.2 CPLD design planning

　　Due to the consideration of the processing capabilities of the microcontroller and CPLD and the system cost, the following plan does not support the linear burst transmission of the PCI bus and other reading and writing methods that require several consecutive data cycles, but only supports the reading and writing of one address cycle plus one data cycle. Way. For most applications, this approach is sufficient. Figure 1 is the simplified PCI bus read and write operation timing sequence.

　　There are 13 8-bit registers in the CPLD to save the data required for a PCI bus read and write, among which pci_address0~pci_address3 are the address data when reading and writing;

Figure 1 Simplified PCI write operation timing

　　pcidatas0~pci_datas3 are the data to be written to the PCI device; pci_cbe[3~0] saves the bus command during the address cycle; pci_cbe[7~4] saves the byte enable command during the data cycle; pci_data0~pci_data3 saves the slave PCI device Returned data; pci_request is the PCI bus read and write operation status register, used to return some information to the microcontroller. When the microcontroller writes a byte to the pci_cbe register, the state machine in the CPLD will be reset, triggering the CPLD to perform read and write operations on the PCI bus; the microcontroller will know that the read and write operations are completed by querying the pci_request register, and then read out from the pci_data register Data returned by the PCI device.

　　The state transition diagram of the state machine in CPLD is shown in Figure 2. Each state corresponds to an output of the FRAME and IRD signals, and other input and output signal lines can be determined by these two signal lines, the value of pci_cbe and the state of TRDY. When FRAME is valid, AD[31~0] is driven by pci_address, and C/BE[3~0] is driven by the lower 4 bits of pci_cbe; when IRDY is valid, C/BE[3~0] depends on the bus command, or Driven by the high 4 bits of pci_cbe, it is either set to a high-impedance state, and AD[31~0] is set to a high-impedance state when pci_cbe[0] is "0" (PCI read command), and when pci_cbe[0] is Driven by pci_datas when "1" (PCI write command). On the other hand, once the TRDY signal line becomes low level, the data on the AD[31~0] line is sent to the pci_data register, and the data on the C/BE[3~0] line is sent to the low level of the pci_request register. 4 bit.

Figure 2 State transition diagram

　　Considering that under abnormal circumstances, the PCI device will not respond to the PCI bus, that is, TRDY will not be effective, in order to prevent the state machine from falling into a stalemate in state S2, a shift counter mycounter is added. When the IRD signal is valid, the counter starts counting. After the count overflows, regardless of whether the PCI bus operation is completed or not, the state machine will transfer from state S2 to state S3, that is, the PCI bus operation ends. When TRDY is valid, mycounter.cout is set immediately.

　　Whether the PCI bus operation is completed correctly can be checked by checking whether the highest bit of pci_request is "1", and the values ​​of IRDY and FRAME can be checked by bits 4 and 5 of pci_request respectively. These two bits reflect the status of the PCI bus operation. When both bits are "1", it can be considered that the PCI bus operation has been completed. In practice, if the microcontroller is not fast enough, it can be considered that PCI bus operations are always completed immediately.

　　2 PCI design interface implementation

　　2.1 CPLD VHDL Programming

　　We designed the program for the 8-bit microcontroller to control the PCI Ethernet card, and used Xilinx's XC95216 series as the CPLD device. The logic has been simplified again according to the characteristics of the Ethernet card. The final program will be adapted into the XC95261 chip and passed in practice.

　　The Ethernet card only supports read and write operations on the configuration space and I/O space, and the addresses of these two spaces can be set within 0xFF, so only one pci_address0 register can be used, and other addresses are directly set to "0"; if As a further limitation, if only one byte of data is written to the network card at a time, only one pci_datas0 register can be used, and other values ​​can be set to the same as the pci_datas0 register during specific operations.

　　2.2 Microcontroller PCI reading and writing C language programming

　　With the help of CPLD, it becomes quite simple for the microcontroller to read and write PCI devices. First, declare registers such as pci_cbe as external memory variables, and specify the address according to the CPLD design. Then, pass the appropriate parameters to the following two read and write sub-functions to complete the read and write operations on the PCI device configuration space, I/O space, and memory space. The return data from the PCI device is stored in the global variable savedata.

　　In fact, when writing to a PCI device, the return data can also be obtained from pci_data. This data must be equal to the data written to the PCI device. This can be used for error checking and fault diagnosis, depending on the specific application.

　　　bdate unigned char request;

　　　sbit IRDY0=request^4;

　　　sbit FRAME0=request^5;

　　　sbit VALID=request^7;

　　　void readpci(unsigned char addr,unsigned char cbe){

　　　pci_address0=addr;

　　　pci_cbe=cbe;

　　　request=pci_request;

　　　while(!IRDY0 & FRAME0)) request=pci_request;

　　　savedata0=pci_data0;

　　　savedata1=pci_data1;

　　　savedata2=pci_data2;

　　　savedata3=pci_data3;

　　　if(!VALID)printf("Data read is invalid! ");

　　　}

　　　void writepci(uchar addr,uchar value0,uchar cbe){

　　　data uchar temp;

　　　pci_address0=addr;

　　　pci_datas0=value0;

　　　pci_cbe=cbe;

　　　request=pci_request;

　　　while(!(IRDY0 & FRAME0)) request=pci_request;

　　　if(!VALID)printf("Data write is invalid!");

　　　}

　　3 Conclusion

　　: CPLD is used to realize parallel communication between microcontroller and PCI bus interface. The circuit structure is simple and small in size. One CPLD chip is enough, and it is easy to control, has strong real-time performance and high communication efficiency. This design method has been successfully used in various data acquisition systems developed by the author, and is used as parallel data communication between the microcontroller and PC104, and the effect is very ideal.

　　4 References

[1] Zhou Mingde. Principles and Applications of Microcomputer Systems[M]. Fourth Edition, Beijing: Tsinghua University Press, 2002.

[2] Bai Zhongying. Principles of Computer Composition[M]. Beijing: Science Press, 1999.

[3] Xilinx chip manual. Xilinx Semiconductor Company of the United States