FPGA System Signal Integrity Simulation Analysis Based on HyperLynx

Abstract: Aiming at the signal integrity problems brought about by the development of high-speed circuits, based on the analysis of signal integrity requirements, with the help of HyperLynx simulation software, the signal integrity analysis and simulation of the system composed of EP2C8 and TMS320F2812 are carried out through the device IBIS model. Based on the reflection principle, the termination method to reduce reflection is introduced, and the design scheme is repeatedly verified by a large number of pre-board and post-board simulations. The research results show that HyperLynx can solve many problems in the signal integrity of the system, and the simulation results provide reference for practical engineering.
Keywords: signal integrity; programmable logic device; HyperLynx; IBIS model

0 Introduction
With the continuous development of high-speed circuits, the clock frequency has long entered the gigahertz era. The reduction of circuit board size and the improvement of device integration make the signal integrity problem more and more important. When the clock frequency exceeds 100 MHz, if the signal integrity requirements of the system are not met, it may cause the system to work unstably and also bring EMC problems. With the increase of FPGA and DSP processing speed, the signal integrity problem is becoming more and more serious, which requires electronic engineers to focus on.
At present, a large number of articles analyze signal integrity from a theoretical perspective, but there are fewer articles analyzing from the perspective of practical application. Based on this, this paper mainly studies the simulation issues involved in the system composed of EP2C8 and TMS320F2 812, and analyzes the signal integrity of the system by simulating the key signal lines.

1 HyperLynx software
HyperLynx is a high-speed simulation tool launched by Mentor Graphics. It can be divided into signal integrity simulation (SI), power integrity simulation (PI) and electromagnetic compatibility simulation (EMC) in terms of content; it can be divided into pre-board simulation (LineSim) and post-board simulation (BoardSim) in terms of structure. In order to ensure the success rate of PCB design, it is important to comply with some good design rules before design. HyperLynx software provides an environment for verifying design methods and testing PCB performance, which will improve work efficiency.

2 System-oriented signal integrity simulation analysis
2.1 System composition and key signals
The system principle block diagram composed of TMS320F2812 and EP2C8 is shown in Figure 1.

Since there are many signal lines in the system, it will take a lot of time to simulate all of them. Therefore, only the key signals need to be simulated. The device rising edge, operating frequency, trace length, clock signal, etc. are used as the conditions for dividing the key signals. It is clear that the high-speed signals include the communication ports of TMS320F2812 and EP2C8, the clock network, the EP2C8 data receiving end, etc. These high-speed signals are susceptible to interference and are easy to interfere with other networks. It is necessary to focus on the design of these signal lines. Through the simulation of HyperLynx, these traces can be optimized and the appropriate design method can be found.
2.2 System board layer design
Before simulating the system, it is necessary to determine the number of PCB stacking layers, trace characteristic impedance, etc., which is the basis for signal integrity simulation of the system. For microstrip lines, the characteristic impedance approximation recommended by IPC is:

Where: h is the distance between the wire and the reference layer; w is the wire width; t is the wire thickness; From the above formula, it can be seen that when w=2h, the trace characteristic impedance is 50 Ω, which can be used as an empirical formula. The system uses a 4-layer circuit board, FR4 material with a relative dielectric constant εr of 4.3, the trace characteristic impedance is set to 50 Ω, the thickness of the PCB board is 1 mm, and the specific stacking scheme is shown in Figure 2.

3 LineSim simulation
LineSim can simulate the designed scheme before layout and routing, and use the simulation results as constraints for actual routing to predict and eliminate signal integrity problems in the early stage.
3.1 High-speed signal line termination simulation
The reason for signal reflection is that when the transient impedance of the signal propagating along the wire changes, part of the signal will be reflected, and the other part will be distorted and continue to propagate, which will cause ringing at the edge of the waveform. Generally, the overshoot amplitude is limited to about 150 mV, otherwise it will cause EMC problems. Typical termination methods include: source end series termination; remote end parallel termination; remote end Thevenin termination; remote end RC termination. Among them, the source end series termination uses fewer devices and has good effect, so the system adopts the source end series termination solution.
Since EP2C8 uses a 20 MHz independent active clock, only the CLK of EP2C8 needs to be considered during simulation. If the output of the active crystal oscillator is directly connected to EP2C8, the LineSim simulation result is shown in Figure 3(a). There is ringing at the edge of the signal, the voltage overshoot amplitude is 3.629 V, and the undershoot value is -450.2 mV, which exceeds the overshoot amplitude range. When a 50 Ω source-end series resistor is used, the SI simulation result is shown in Figure 3(b). The clock signal received by the receiving end has no ringing at the transition point, and the effect of suppressing signal reflection is very good.

Crosstalk is one of the signal integrity issues. It refers to the transfer of harmful signals from one network to an adjacent network. Crosstalk can be divided into near-end crosstalk (NEXT) and far-end crosstalk (FEXT). The reflection of the transmission line is also related to crosstalk. The use of appropriate source termination and far-end termination can reduce crosstalk to a certain extent. However, crosstalk is related to capacitive coupling and inductive coupling between signals. Crosstalk cannot be completely eliminated, but can only be reduced. There are a large number of high-speed data lines between TMS320F2812 and EP2C8. If they are not processed, it is possible to receive erroneous data. Figure 4 shows the results of SI simulation of data lines D8, D9 and D10 using LineSim. D9 is set as the interfered network, D8 and D10 are the attacking networks, the oscillation frequency is 20 MHz, and the termination resistance is 50 Ω. It can be seen from the figure that D9 is less interfered with, and the overshoot voltage is only 122 mV. If you want to further reduce crosstalk, you can reduce the trace width to 8 mil and shorten the trace coupling length.

[page]

3.2 High-speed signal line timing problem
The data transmission rate between TMS320F2812 and EP2C8 is high, so the timing becomes very important. If the time difference between the two signals reaching the receiving end is close to one acquisition cycle, it will cause wrong data to be received. In order to avoid this timing problem, the serpentine line is used to ensure the consistency of the high-speed signal routing length, as shown in Figure 5. The PCB design tool is Altium's DXP 2004.

4 BoardSim simulation
BoardSim is a simulation performed after the PCB is drawn. It generates a full-page report to verify the rationality of the original design and correct the layout and routing. The simulation will use the IBIS model of the device to simulate the designed PCB routing, including signal integrity, EMC, timing, etc.
4.1 Crosstalk simulation verification
In Section 3.1, crosstalk simulation has been performed on D8, D9 and D10. Now use BoardSim to verify the above simulation results. Considering that the actual resistance value is not 50 Ω, the termination resistance value is 51 Ω and the oscillation frequency is 20 MHz. Figure 6 shows the interference to D9 when D8 and D10 have data communication. As can be seen from the figure, the waveform jitter at D9 is very small, the crosstalk voltage overshoot is only 44.8 mV, and the undershoot voltage is only -39.8 mV, which basically does not affect the signal of D9. The results show that the signal integrity check has been passed.

4.2 Termination simulation verification
Mainly verify the rationality of the termination scheme of the clock signal and data line.
4.2.1 Termination of the clock signal
The clock signal network is labeled CLKIN, and the termination resistor value is 51 Ω. The results of SI simulation are shown in Figure 7. It can be seen that the simulation in BoardSim is almost the same as that in LineSim, which meets the SI requirements.

4.2.2 Termination of data lines
Although serpentine lines can solve the timing problem of signals, it should be noted that serpentine lines have a certain impact on signal integrity. The smaller the spacing of the serpentine lines and the longer the coupling length, the greater the crosstalk of the signal, so this point needs to be taken into consideration during design. Table 1 shows the lengths of the 16 data lines D0 to D15 between EP2C8 and TMS320F2812. The shortest network is D14, which is only 2.661 inches, and the longest is D7, which is 2.856 inches. The length variation is controlled within (2.76±0.1) inches. The SI simulation results are shown in Table 2.
Table 2 shows the batch simulation results of SI for data lines by BoardSim. It is found that the specific delays of the rising and falling edges of the 16 data lines are basically the same, indicating that the quality and delay requirements of the signal receiving end are guaranteed by correct termination and equal length lines. Then, batch EMC simulations were performed on these data lines. The simulation standards were FCC and CISPR. The result was Net\'s EMCis within selected limits. It can be seen that the system meets the EMC requirements.

5 Conclusion
This paper uses HyperLyn software and IBIS models of components to perform signal integrity simulation analysis on the TMS320F2812 and EP2C8 systems. Through analysis, it can be seen that appropriate termination resistance can greatly reduce the reflection and crosstalk of the signal on the wire. The serpentine routing solution solves the delay problem of high-speed data lines. After the routing length is matched, the specific time of the rising/falling edge of the data line is basically the same, which meets the SI requirements.