Design of EPA Field Controller Based on SOPC Technology

introduction

With the rapid development of Ethernet technology, industrial Ethernet has gradually become the mainstream high-speed communication method in automation control systems, and industrial Ethernet technology has become an independently developed branch. EPA is my country's first industrial automation standard with independent intellectual property rights and accepted and adopted by the International Organization for Standardization. This standard is an industrial control network communication standard based on information network communication technologies such as Ethernet, wireless LAN, and Bluetooth, and is suitable for data communication between industrial automation control system devices and instruments, and between industrial automation instruments.

A large number of EPA field devices communicate by installing EPA communication cards, and most of the processors of these communication cards use ARM cores. In recent years, with the rapid development of semiconductor technology, the traditional chip design method is undergoing a revolution, which is marked by the fact that the system-on-chip (SoC) has been widely accepted by the industry and has become a hot spot for research and development. SOPC technology has emerged with the emergence of SoC technology. It combines the advantages of SoC and FPGA, is scalable, expandable, and upgradeable, and has the function of software and hardware programmable in the system. SOPC can provide better performance and lower power consumption, effectively save circuit board space and reduce the total cost of the product. The electronics industry is gradually shifting to SOPC design, making SOPC one of the best choices for modern electronic systems. Based on a thorough study of EPA network communication and SOPC technology, an EPA controller based on SOPC technology has been developed.

SOPC Technology

SOPC technology was first proposed by Altera in the United States in 2000, and the corresponding development software Quartus II was launched at the same time. SOPC is a SoC based on FPGA solution. Compared with ASIC SoC solution, SOPC system and its development technology have more features and the following basic characteristics: at least one embedded processor IP core; small-capacity on-chip high-speed RAM resources; abundant IP core resources for flexible selection; sufficient on-chip programmable logic resources; processor debugging interface and FPGA programming interface share or coexist; can contain some programmable analog circuits; single chip, low power consumption.

SOPC is a new system design technology and also a new hardware and software integrated design technology. Through it, the hardware system (including microprocessor, memory, peripherals and user logic circuit, etc.) and software design can be quickly placed in a programmable FPGA chip to achieve the IC design of the system. This design method has the advantages of short development cycle and system modifiability. The designed SOPC can be converted into ASIC chip through HARDCOPY, so as to achieve rapid mass production.

EPA Field Controller Design

Aiming at the requirements of connecting the management network, control network and field equipment units in the control system, a controller suitable for EPA industrial Ethernet is designed by using SOPC technology, fieldbus technology and automatic control technology, and a real-time operating system and EPA communication protocol stack are implemented on its editable soft-core CPU processor. The EPA field controller can realize the input and output of real-time control information, and monitor, display and alarm other EPA devices on the Ethernet. This article will explain the CPU core processing module and communication processing module based on SOPC technology of the EPA controller respectively.

Overall Hardware Design Scheme for EPA Field Controller

Figure 1 is the hardware system structure block diagram of the EPA field controller. In the entire design, the hardware implements the design of the peripheral interface circuit of the EP1C12Q240C8 chip and the LAN91C111 chip; the design of the serial communication and network communication; the design of the reset circuit, JTAG, clock circuit, and power circuit; the design of the keyboard circuit, LCD display circuit, and buzzer alarm circuit; the design of the peripheral circuit of the HY57V641620 chip and the AM29LV160 chip, and expands the rich memory resources, which can be transplanted to the Linux and Windows CE operating systems; expands the bus interface, and can connect to the corresponding boards according to the actual needs of the industrial site (such as DI/DO modules, AI/AO modules, to achieve digital-to-analog and analog-to-digital conversion between field data, expand the MMC memory card, expand its storage capacity, etc.).

Figure 1 Hardware structure diagram of EPA controller based on FPGA

During the design, the controller's structure and functions are complex, and many types of devices are involved. Therefore, the hardware board is divided into two parts during the design. The first part: CPU core processing module, including CPU processor EP1C12Q240C8, memory (FLASH, SDRAM), power supply, clock source, JTAG, EPCS download port and reset circuit. The second part: communication processing module, including network communication (LAN91C111 network card chip and RJ45), serial communication (MAX3232), LCD interface, keyboard interface and buzzer. [page]

CPU core processing module based on SOPC technology

The whole scheme is realized for the purpose of accessing the real-time industrial Ethernet network, realizing part of the EPA protocol inside the chip, and the controller realizing the monitoring, display and data analysis of other devices on the industrial Ethernet. The design adopts Altera's new generation of low-cost FPGA chip EP1C12Q240C8 chip, which contains 12060LE (logic unit). According to actual needs, it can be configured with its NIOSⅡCPU soft core, on-chip peripherals and memory connected to the CPU, and interfaces connected to off-chip memory and off-chip devices. The block diagram of the chip system structure is shown in Figure 2.

Figure 2 Chip system structure block diagram

The hardware and software design of the entire CPU processor is implemented on the Quartus II 5.1 version. The NIOSⅡ processor core is Altera's second-generation user-configurable general-purpose 32-bit RISC soft-core microprocessor. It is Altera's unique configurable soft CPU core based on FPGA architecture. Its features and peripherals can be increased or tailored according to actual needs. All NIOSⅡ processor systems use unified instructions and programming models, and there are three types to meet the requirements of different designs, namely fast type, economic type and standard type. In this controller, the customized NIOSⅡ soft core uses the fast type. The core processing speed is 49DMIPS, the number of logic gates consumed is 1400~1800LE, and it also has a hardware multiplier and a hardware divider. According to the requirements of the EPA network for the controller, add on-chip peripherals and off-chip device interfaces connected to the CPU: SDRAM controller, on-chip RAM, tri-state bridge, UART, timer, general I/O port, LCD display driver circuit and Ethernet interface. According to the design requirements, the CPU configuration in Quartus II 5.1 is shown in Figure 3. FPGA chips can flexibly add functions according to actual needs, and unnecessary functions can also be deleted to meet the requirements of fast, efficient and low-cost design.

Figure 3 EP1C12Q240C8 chip configuration

After configuring the internal structure of the CPU processor, configure the CPU periphery according to the design requirements. Since the controller is connected to the EPA network, the EPA protocol needs to be implemented, and the FPGA chip EP1C12Q240C8 has only 288K of RAM inside, so 16M bits of FLASH-AM29LV160D and 64M bits of SDRAM-HY57V641620 are expanded outside the chip. A 12V DC power supply is introduced from the outside, and after level conversion, 3.3V and 1.5V power supplies are obtained to power the CPU, memory and other powered devices. The clock source on the CPU uses a 50MHz clock oscillator. JTAG and EPCS download ports are used to download hardware and software. The hardware program and software program edited on Quartus Ⅱ are downloaded to FLASH and RAM (on-chip or off-chip) through the JTAG and EPCS download ports for online debugging. The reset circuit is composed of a 10KW resistor, a 10mF capacitor and a button, which can realize a low-level reset by a button and a low-level reset by power on. [page]

Communication processing module

The entire design uses the FPGA chip EP1C12Q240C8 as the data processing center, and completes data communication with other devices on the industrial Ethernet through network communication. At the same time, the serial port communication with the host computer is realized through MAX3232. In this module, LCD interface, column keyboard interface and buzzer interface are added to monitor and display other EPA devices on the industrial Ethernet, and it has a good human-computer interaction function.

In this design, network communication is divided into two communication modes: wired and wireless. Among them, the wired network communication uses the 10M/100M LAN91C111 adaptive network card chip and accesses the EPA network through the RJ45 network port. LAN91C111 is the third-generation Fast Ethernet controller launched by SMSC for embedded application systems. The LAN91C111 chip integrates the MAC (media layer) and PHY (physical layer) that follow the SMSC/CD protocol and complies with the IEEE802.3/802.U-100Base-Tx/10Base-T specification. The wireless communication interface of the Bluetooth module and the ZigBee module is reserved on this controller as an auxiliary processing module. According to the actual situation of the industrial site, the wireless communication module can be connected to realize wireless communication with the EPA network. Through this module, the operation status and related parameters of the wireless field equipment can be monitored.

In the entire EPA communication protocol stack network layer and transport layer receiving message processing flow. After the NIOSⅡ processor is reset, it initializes the UC/OSⅡ operating system, network interface, stack, and peripheral device interfaces such as timers. Obtain network information such as IP address and MAC address from the external memory FLASH. When the IP address and MAC address of the received message are both local addresses, the message is stored in the receiving buffer in the form of a special structure required by LWIP, and then sent to the EPA protocol stack for processing. When the UDP port number is checked to be 0x88BC, the message is handed over to the EPA application layer processing module for processing.

Figure 4 EPA protocol stack receiving message processing flow chart

Some of its message processing procedures are as follows:

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Conclusion

After the whole design is completed, the controller can be connected to the EPA network and operate normally. Since the processor in the controller uses FPGA chip, it has strong flexibility and can be programmed, debugged, reprogrammed and repeated, so it can be fully designed, developed and verified. When there are small changes to the circuit, its advantages are more prominent. Its on-site programming ability can extend the life of the product in the market and can be used for system upgrades, thereby greatly improving the performance of the controller.