Application of CPLD and EPP technology to high-speed acquisition of CCD signal at pixel level

Preface

CCD (Charge Coupled Device), or charge coupled device, is a new type of solid-state imaging device developed in the early 1970s. With the help of necessary optical systems and appropriate peripheral drive and processing circuits, CCD chips can convert, store and transmit scene images through point-by-point photoelectric signals on the input surface space, generate a time-series video signal at its output end, and synchronously display the image visible to the human eye through the terminal monitor. With the rapid development of CCD technology, the acquisition of CCD signals and how to communicate information with computers after the acquisition have become an important issue in CCD applications. The ability to perform high-speed acquisition of each pixel of the CCD and transmit it to the computer for processing in real time will greatly improve the accuracy of the collected CCD signals and solve the problem of real-time processing.

EPP technology and CPLD technology

EPP technology (Enhanced Parallel Interface Technology) can perform high-speed bidirectional data transmission. It can distinguish two types of information and define them as data and address respectively. It can also achieve high-speed direction conversion, so it is very suitable for the field of data acquisition. EPP can complete the reading and writing of one byte of data, including handshake, in one ISA bus cycle. The data line is bidirectional. One control signal is responsible for determining the direction of the data port, and the other two control signals are used to distinguish the data and address information on the data line. EPP transmission can automatically generate control signals and detect the other party's response. EPP mode supports 4 operations, namely address writing, data writing, address reading and data reading. Data reading and writing are generally used for data transmission between the host and the peripheral, and address reading and writing are generally used for the transmission of address, channel, command and control information. When the EPP mode wants to write a data byte, the data needs to be written to the EPP data register. The write operation will cause the interface to start a complete data write cycle. The hardware of the interface puts the data to be written in D0~D7, and then the interface automatically triggers the handshake signal and detects the response of the peripheral. Reading 1 byte is similar to this. Reading the EPP data register will trigger a complete data read and write cycle. The address transmission process is basically the same as the data transmission process. The base address of EPP is usually 378h, and the addresses used by the interface are 378h to 37fh.

CPLD (Programmable Logic Device) technology can integrate digital circuits into a chip, greatly reducing the size of the circuit board, and its programmability makes the designed circuit very simple and convenient to upgrade and modify. In the acquisition system, the above two technologies will be used and combined with A/D (Analog-to-Digital Converter) and FIFO (First-in-First-out Buffer) to design, which well solves the problem of CCD signal acquisition and processing.

System composition and basic principles

The CCD signal acquisition system consists of the following parts: CCD digital sensor, A/D, FIFO, CPLD, and computer, as shown in Figure 1.

When the A/D receives the CCD signal and converts the voltage value of each pixel of the CCD into a 12-bit digital value, it is sent to the FIFO. The speed mismatch problem between the FIFO and the A/D is solved through the logic control of the CPLD, and the data transmission of the FIFO is controlled to the computer parallel port.

CPLD controls the entire acquisition system, including 2-to-1 data selection circuit, working trigger circuit, CCD integration time selection circuit, and FIFO working state control circuit. The circuit diagram is shown in Figure 2. When the acquisition is ready, the acquisition enable pulse of the CCD initializes each chip of the acquisition card. After that, the acquisition pulse of the CCD sends an acquisition pulse to the AD through the ENCODE terminal of the AD. When the AD completes one acquisition, the DAV sends a high pulse, which serves as the write pulse signal of the FIFO. At the same time, the acquisition pulse also sends a counting pulse to the counter in the digital comparator. The parallel port detects the number of acquisition pulses and read pulses at the same time. When the number of read pulses is less than the number of acquisition pulses, the parallel port reads data from the FIFO. This can ensure that there is no data left in the FIFO, and it can also ensure that the read and write pulses can end in the shortest time, greatly shortening the acquisition time. After one acquisition is completed, wait for the CCD to issue the instruction for the next acquisition. When the parallel port reads data from the FIFO, the data will be read in two parts each time, half of the total number of bits will be read each time, and high and low identification bits will be added so that the computer can identify the high and low bits respectively after the data is read into the computer. [page]

Choosing the right chip in the acquisition system will make the acquisition speed of the acquisition system reach the maximum transmission speed of the parallel port, and the maximum accuracy can reach 14 bits. Since the acquisition system communicates with the computer through the parallel port, it avoids the electromagnetic interference of the computer hardware electronic devices on the acquisition card, so it has good anti-interference performance.

Driver for the acquisition system

VC++ has very powerful underlying operating capabilities. It can easily realize the reading, writing and operation of the parallel port, and it is also very convenient to analyze and process the collected signals later. VC++ encapsulates the dynamic link library (DLL) as the driver of the acquisition system, which mainly encapsulates the following functions.

BOOL PASCAL EXPORT PTC_Open (PTC_HANDLE *phPTC); //Open the parallel port

void PASCAL EXPORT PTC_Close(PTC_HANDLE hPTC); //Close the parallel port

BYTE PASCAL EXPORT PTC_Readdata (PTC_HANDLE hPTC); //Read parallel port data register

void PASCAL EXPORT PTC_Writedata (PTC_HANDLE hPTC, BYTE data); //Write parallel port data register

BYTE PASCAL EXPORT PTC_Readstatus (PTC_HANDLE hPTC); //Read the parallel port status register

BYTE PASCAL EXPORT PTC_Readcontrol (PTC_HANDLE hPTC); //Read parallel port control register

void PASCAL EXPORT PTC_Writecontrol (PTC_HANDLE hPTC, BYTE data); //Write the parallel port control register. The detailed code is not listed one by one due to space constraints.

Conclusion

By utilizing the synchronization of the CCD signal acquisition pulse signal and the data input signal, the acquisition card can realize the acquisition of each pixel of the CCD signal, so that the acquired data can reach a very high precision, and different FIFO reading methods can be realized by flexibly changing the main control circuit of the CPLD to meet the requirements of different jobs. In addition, the speed and precision of the FIFO are very high, and better acquisition effects can be achieved by replacing high-speed, high-precision AD. It is best to communicate with the computer through the parallel port to avoid the influence of the computer's internal circuit on the CCD signal, and also greatly improve the acquisition effect.