FPGA Implementation of Digitally Controlled Oscillator (NCO)

Publisher:风轻迟Latest update time:2011-04-29 Source: 电子技术应用Keywords:NCO  FPGA Reading articles on mobile phones Scan QR code
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Abstract: The working principle of NCO digital controlled oscillator is introduced, and the performance index of digital controlled oscillator and its implementation method in FPGA are analyzed in detail. Finally, the simulation results of the newly designed digital controlled oscillator in QUARTUSII are given.
Keywords: Numerically Controlled Oscillator (NCO); Spurious Free Dynamic Range (SFDR); FPGA; Frequency Control Word

0 Introduction
NCO (Numerically Controlled Oscillator) is a digital controlled oscillator used to generate an ideal, digitally controllable sine or cosine wave. There are many implementation methods such as real-time calculation method and table lookup method. The sine wave samples of the real-time calculation method are generated by real-time calculation. Because this method takes a lot of time to calculate, it can only generate a sine wave with a lower frequency, and there is a contradiction between calculation accuracy and calculation time. Because the real-time calculation method cannot be realized when it is necessary to generate high-speed orthogonal signals. Therefore, in practical applications, the most effective and simple table lookup method is generally used, that is, the sine value of the phase is calculated in advance according to the phase of each NCO sine wave, and the sine value data of the phase is stored according to the phase as the address information.

1 Basic principles of NCO
When generating address information through phase accumulation, it is usually necessary to output the sine value corresponding to the phase value at the current moment, that is, to sample the phase at equal controllable intervals with a reference frequency source. As we all know, the ideal sinusoidal signal S(t) can be expressed as:
a.JPG
Formula (1) shows that after the amplitude A and the initial phase φ of the signal s(t) are determined, its frequency can be uniquely determined by the phase. That is:
b.JPG
NCO uses the principle that φ(t) and time t in formula (2) are linearly related to perform frequency synthesis. That is, within the time interval t=△t, the phase increment △φ of the sinusoidal signal and the frequency f of the sinusoidal signal can form a one-to-one correspondence. That is, after differentiating both ends of formula (2), we have: c.JPG .
From the above discussion, we can see that:
i.jpg
Among them, △θ is the phase increment between a sampling interval △t, and the sampling period d1.jpg . Therefore, formula (3) can be rewritten as:
d2.jpg
From formula (4), we can see that if △θ can be controlled, different frequency outputs can be controlled. Since △θ is controlled by the frequency control word FCW, that is: d4.jpg , so changing FCW can get different output frequencies f0, and then the following equations can be obtained by substitution:
d3.jpg
L in equations (5) and (6) is the number of bits of the phase accumulator. According to the Nyquist criterion, the maximum output frequency allowed is FCLK/2, that is d5.jpg . However, in actual engineering, due to the limitation of the low-pass filter, the output frequency is d.JPG generally



2 NCO performance indicators
The performance indicators of NCO include signal frequency resolution, signal-to-noise ratio (SNR), spurious-free dynamic range (SFDR) and output signal orthogonality. These performance indicators depend on the number of data bits of the NCO. The number of data bits of the NCO includes the number of bits n used to represent the phase data and the number of bits nb used to represent the sine value data of the phase. There is a relationship between the two that nb depends on n, and the former must be able to represent the minimum and maximum values ​​of the change in the sine value of the phase when the phase changes. This can be divided into two cases:
the first case is that the minimum change of the sine value of the minimum phase change occurs at π/2-△φ~π/2, π/2~π/2+△φ, 3π/2-△φ~3π/2, 3π/2~3π/2+△φ, and the phase value is between 0 and 2π and is equally spaced into 2n points. Therefore, according to the characteristics of the sine wave, it can be seen that only the difference between the sine values ​​of the phase at the π/2-△φ and π/2 points needs to be discussed:
e1.jpg
the second case is that the maximum change of the sine value of the minimum phase change occurs at 0~△φ, π-△φ~π, π~π+△φ, 2π-△φ~2π points. This case can be obtained by a derivation method similar to the first case:
e.JPG
when designing, n and nb can be well selected according to equations (9) and (10) to avoid the phase resolution from being blunted and to meet the design requirements well.
The noise of NCO is introduced by the quantization error of the sine value, and the quantization error is determined by the number of bits representing the sine value. The approximate relationship is:
f.JPG
Where B is the number of truncated bits used as the address of the addressing ROM, and n is the number of phase bits. Another performance parameter of NCO is the frequency resolution △f, which depends on the number of phase bits. The relationship is:
g.JPG

3 Implementation of NCO in FPGA
The lookup table of NCO is a sine value table. The sine values ​​of the table are stored according to the phase as the storage address, and are generally stored in a phase increment manner. Using the odd-even symmetry of the sine wave, the 2π phase can be divided into 4 equal parts, and then the symmetry between the equal parts is used to realize the mapping of address information. Usually only the amplitude code in the [0, π/2] quadrant is stored.
The phase accumulator can complete the phase accumulation, that is, φ=φ+△φ is accumulated once for every clock, and it works in a pipeline manner. This design uses a 32-bit accumulator that comes with the IP core in QUARTUS II to achieve phase accumulation. After the logic conversion is completed, the small table structure function block can be used to convert the highest 2-bit signal generated by the phase accumulator into an address control signal and a quadrant conversion control signal. The address control signal is based on the highest two-bit signal to control whether the address is generated in an increasing manner from 0 or in a decreasing manner from 2L. The sine table outputs a sine value data greater than zero for each clock. These data can be used as the input of the quadrant converter, and the quadrant converter completes the quadrant conversion of the data. The conversion principle is: the quadrant control signal converts the data obtained from the table into positive and negative data according to the symmetry of the sine signal, and adds zero to the 1st and 2nd quadrant data of the sine signal, and performs complement operation on the data of the 3rd and 4th quadrants. The same is true for the cosine data. The data is added to zero in the 1st and 4th quadrants, and the data of the 2nd and 3rd quadrants are complemented. 4 Simulation results The NCO implemented using the above small table structure can output multiple frequency signals and reduce resource consumption. The factors affecting the output frequency of the system are mainly the operating frequency and device performance. FIG1 shows the simulation waveform of the entire NCO in QUARTUS II.





h.JPG


In the waveform shown in Figure 1, CLK is the clock input frequency (65.6 MHz), CLR is the system reset signal, the number of bits of the phase accumulator L is 32 bits, the number of bits of the output signal amplitude is 12 bits (including the sign bit), and the phase width is 12 bits. Thus, from equation (5), the frequency control word FCW is 269591793. COS_OUT and SIN_OUT in Figure 1 are the system output signals with a frequency of 4.08 MHz.
From equations (11), (12), and (13), the signal-to-noise ratio and SFDR of this system are 74 dB and 84 dB respectively.
Figure 2 shows the waveform displayed when the sine and cosine data in the waveform file are read into MATLAB.

5 Conclusion
This paper analyzes the implementation principle and performance of the numerically controlled oscillator, and gives a specific method to implement NCO through FPGA. At the same time, the correctness of this design is verified by simulation in QUARTUSⅡ. The results show that the NCO designed by this method can output signals of multiple frequencies and reduce resource consumption.

Keywords:NCO  FPGA Reference address:FPGA Implementation of Digitally Controlled Oscillator (NCO)

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