Multimode blind equalization algorithm based on point decision domain and its FPGA implementation

Abstract: The constant modulus algorithm cannot overcome the phase distortion problem of the signal, and the steady-state error is large; the modified constant modulus algorithm can restore the signal phase, but after the equalizer converges, the steady-state error is still large. To address this problem, a multi-mode blind equalization algorithm based on point domain decision is proposed. The algorithm uses the decision value of the signal to reduce the steady-state error of the equalizer without increasing the complexity of the equipment. The FPGA design scheme of the multi-mode algorithm is given. Based on the ISE design platform of Xilinx, the timing simulation analysis is carried out in Modelsim and compared with the MATLAB simulation. The experimental results show that the blind equalizer can overcome the amplitude and phase distortion of the signal, and has the advantage of low steady-state error.

Keywords: constant modulus algorithm; modified constant modulus algorithm; multi-modulus algorithm; FPGA implementation

Blind equalization has been widely used in high-speed satellite communication systems because it does not require the use of training sequences and effectively improves the utilization of frequency bands. Among various blind equalization algorithms, the constant modulus algorithm (CMA) [1] has attracted much attention due to its simple implementation and stable performance. CMA only uses the amplitude characteristics of the signal and cannot overcome the phase distortion problem. The modified constant modulus algorithm (MCMA) proposed in reference [2] can restore the signal phase, but the improvement of steady-state error performance is limited. Based on the above references, this paper proposes a multi-mode blind equalization algorithm based on point decision domain partitioning.
With the development of FPGA device scale and processing speed, its application in the field of digital signal processing is becoming more and more extensive. References [3, 4] discuss the application of FPGA in digital modulation and carrier tracking. This paper uses the ISE design platform of Xilinx to design and implement the multi-mode blind equalization algorithm on FPGA so that it can be applied in actual satellite communication systems.

The update equation of the equalizer weight coefficient vector adopts the stochastic gradient descent algorithm of formula (2).
Figure 1 shows the equalization principles of the three algorithms. Figure 1 (a) is the working principle of CMA. CMA makes the output of the equalizer approach the circle of fixed radius in the figure. It only considers the amplitude information of the signal, so the steady-state error is large after the equalizer converges; Figure 1 (b) is the working principle of MCMA. MCMA makes the real part of the output signal approach the left and right lines, and the imaginary part approaches the upper and lower lines. The algorithm considers the phase information of the signal, so it can overcome the phase distortion caused by channel characteristics and carrier offset; Figure 1 (c) is the working principle of MMA. The equalizer makes the channel output approach the closest constellation point, so after the equalizer converges, the minimum steady-state error can be obtained.

[page]
2 FPGA Design of Multi-mode Algorithm
The XC3-S1600E device from Xilinx's Spartan 3E series was selected, and the ISE9.1i integrated development environment was used for synthesis and implementation. The third-party software modelsim was used for simulation, and the VHDL hardware description language was used to implement the multi-mode blind equalizer.

2.1 Equalizer structure design and function description
The structure of the multi-mode blind equalizer is shown in Figure 2.

(1) Source module: A linear feedback shift register is used to generate a pseudo-random sequence, and the characteristic polynomial of the sequence is f(x)=1+x3+x7. After serial/parallel conversion, the 4 bits of each channel are mapped to the corresponding level sequence to form the in-phase and orthogonal signals of 16QAM.
(2) Filter module: The filter module includes a channel filter and an equalizer. The channel impulse response and the equalizer weight coefficients both adopt the FIR filter structure. In order to save hardware resources, the FIR filter is implemented in a serial structure. The channel filter adopts a FIR filter with fixed coefficients, and the equalizer adopts a FIR filter with adjustable coefficients.
(3) Decision module: The decision device makes a decision on the output of the equalizer, and uses the minimum distance criterion to find the point closest to the equalizer output in the character set of the 16QAM constellation diagram as the decision value of the current signal point.
(4) Error calculation and coefficient update module: The iterative error is calculated according to formula (12), and the coefficient update adopts the steepest descent method of formula (2).

2.2 Data Format and Truncation
In FPGA, signals and numbers are represented by binary fixed-point signed numbers, and fixed-point values ​​are represented by two's complement [5]. The data formats of the signals and variables involved in the algorithm are shown in Table 1.

During the algorithm execution, the source signal s(k), channel coefficient h(k), channel output x(k), equalizer output y(k), and decision output d(k) are all represented by 8-bit word length; the error signal e(k), equalizer coefficient w(k), and step factor are represented by 16-bit word length; the mean square error mse(k) is represented by 32-bit word length.
In the case of limited word length, addition and multiplication operations will increase the bit width of the operands. In order to save hardware resources, the data after the multiplication operation is effectively truncated. Since the signal energy and channel coefficients are normalized, there is no overflow during the operation, which ensures the accuracy of the operation results.

3 MATLAB simulation and FPGA implementation
The algorithm is simulated and analyzed for the 16QAM system. The number of taps of the equalizer is 7, the center tap weight is initialized to 1, and the other tap weights are initialized to zero. The channel parameters of the satellite channel are: the amplitude-frequency response meets the Nyquist raised cosine characteristic, the group delay distortion is 2.25 codeword widths, the channel length is 6, and the FIR coefficient is:

Figure 3 shows the comparison of the convergence speed of the three algorithms. The channel signal-to-noise ratio is 25 dB, and the curve is obtained through 100 independent Monte Carlo simulations. It can be seen from the figure that the steady-state error of CMA is about -6 dB, the steady-state error of MCMA is about -12 dB, and the steady-state error of the multi-mode algorithm reaches -21 dB, which is very obvious compared with the first two algorithms. The iteration speed of the three algorithms is about 4,000 codewords.

Figures 4(a) and 4(b) are obtained by Matlab simulation and modelsim simulation respectively, and the clock cycle of FPGA is 50 MHz. The figure shows the iteration of the mean square error of the first 100 code elements of the multi-mode blind equalization algorithm. As can be seen from the figure, the results of the two are consistent, indicating the correctness of the FPGA design.

Figure 5 is a waveform diagram after the equalizer converges. The four waveform curves are the in-phase components of the transmitted code element, channel output, equalizer output, and decision device output from top to bottom. After the signal passes through the channel, it is severely distorted, namely, inter-code interference; after passing through the equalizer, the interference between code elements is eliminated, and it is very close to the transmitted code element waveform; the decision device judges the equalizer output according to the minimum distance criterion and obtains the correct code element output.

This paper proposes a multimode blind equalization algorithm based on point domain decision, and gives the FPGA design and implementation scheme of the equalizer. Compared with the CMA equalizer, the steady-state error of the multimode blind equalizer is improved by about 15 dB, and compared with the MCMA equalizer, the steady-state error is improved by about 9 dB. After the equalizer converges, it can overcome the amplitude distortion and phase distortion of the signal and correctly restore the information of the transmitter.