Computer Design and FPGA Implementation of High-Order FIR Filters

Abstract: Based on the principle of finite impulse response (FIR) digital filter, a FIR filter design method using parameterized macro function module (LPM) in QuartusⅡ is proposed by combining Matlab and QuartusⅡ of FPGA. First, the filter coefficients are designed by Matlab, and then the multipliers and adders constructed by LPM of QuartusⅡ are used to obtain the filtering results. Compared with the distributed algorithm, this method can achieve the filtering effect more simply when the signal processing rate is not high and the filter order is high. Finally, based on Matlab and QuartusⅡ, the design and simulation of 64-order high-order FIR digital filter circuit are realized.
Keywords: FIR filter; Matlab QuartusⅡ; parameterized function module library

Compared with infinite impulse response (IIR) filter, finite impulse response (FIR) can obtain strict linear phase characteristics while satisfying the amplitude-frequency response of the filter. Data communication, voice signal processing and other fields often require that the signal should not have obvious phase distortion during transmission, so FIR filter has been more widely used. There are many methods for designing and implementing FIR filters. The most commonly used one is the FIR filter design based on distributed algorithm. This method uses the construction of a lookup table and pipeline operation to complete the filtering process, which greatly improves the processing efficiency of the system. However, the system memory capacity required by the lookup table increases exponentially with the order of the filter. Based on engineering practice, this paper proposes a FIR filter design method based on LPM parameterized macro function module when the signal processing rate requirement is not high and the filter order is high. It has certain engineering practical value.

1 Principle and design method of FIR filter
1.1 Principle of FIR filter
The mathematical expression of FIR filter is:

Where: N is the number of taps of FIR filter; x(n) is the input sample at the nth moment; h(k) is the tap coefficient of the kth stage of FIR filter.
The structure of direct FIR filter is shown in Figure 1.

As shown in Figure 1, the FIR filtering process is a process of signal delay at each level. The delayed outputs of each level are weighted and accumulated to obtain the FIR output. The most important algorithm is the multiplication-accumulation operation. Since each FIR filtering process requires N multiplications and N-1 additions, the amount of FIR filtering operations depends entirely on the size of N.
1.2 Distributed FIR filter design
The distributed algorithm (DA) was proposed by Croisier as early as 1973. It was not until the appearance of the lookup table (LUT) structure of the field programmable gate array (FPGA) that this algorithm was re-emphasized. Its main principle is as follows.
For the sake of simplicity of analysis, the expression (1) of the FIR filter is rewritten as:

It can be seen that the distributed algorithm is an optimization solution for the purpose of realizing the "multiplication-addition" unit. A lookup table (LUT) is used to implement the mapping, that is, a 2k word width (i.e., 2k rows) is used to pre-program the mapping of a K-bit input vector Xb=[X0b, X1b, …, X(k-1)b] received by the LUT in the program, and the partial product is directly output after the lookup in the lookup table . However, as can be seen from the above, the word width of the lookup table is 2k. If the tap coefficients of the filter are too many, the scale of the lookup table will increase exponentially with the increase of the tap coefficients, which will make the scale of the LUT very large. In order to reduce the scale, the partial table calculation method can be used, that is, a large lookup table can be divided into several small lookup tables, and then the results are added.
1.3 FIR filter design based on LPM parameterized macro function module
As can be seen from Section 1.2, the distributed algorithm greatly reduces the scale of the hardware circuit and is easy to implement pipeline technology, which not only improves the execution speed of the circuit, but also greatly improves the signal processing efficiency. However, when the processing speed required by the system is not high, the LPM parameterized macro function module in QuartusⅡ can be used to design FIR filters; when the filter coefficient is large, this method does not need to construct a huge lookup table or multiple small lookup tables like the distributed algorithm.
1.3.1 Brief description of LPM parameterized function module
LPM is the abbreviation of the library of parameterized modules. Designers can select appropriate modules in the LPM library according to the needs of the actual circuit and set appropriate parameters for them to meet the design requirements. Commonly used LPM macro function modules include arithmetic components such as accumulators, adders and multipliers; multiplexers and LPM gate functions also have gate circuits such as I/O components, memory compilers, etc. Users can refer to relevant information according to their own needs. This article uses the multiplier and accumulator to complete the design of FIR filters. 1.3.2
Design of FIR filter
In QuartusⅡ, the "Megawizard" wizard is used to generate the required modules, and its interface is shown in Figure 2.

Select LPM_MULT in Arithmetic on the left side of the figure to get the interface of Figure 3. Select appropriate parameters according to the technical indicators to generate the multiplier module. Follow the wizard to complete the setting of the multiplier parameters (such as the number of bits of the multiplier, whether to multiply signed numbers, etc.). The structure of the adder module is similar and will not be described in detail.

Taking the FIR filter designed in this paper as an example (described in detail later), the input signal rate is 2 MHz (period is 500 ns), and the filter order is 64. Therefore, 8 multipliers are constructed (up to 25 can be constructed) to complete all multiplications in 8 times. Compared with the pipeline speed of the distributed algorithm, the constructed multiplier takes 20 ns to complete a multiplication, which is relatively longer, but it only takes 8×20=160 ns to complete 8 multiplications, which is less than the time of one cycle of the input signal, so it meets the design requirements. Divide one cycle of the input data into 8 time blocks on average, and the block diagram of the FIR filter design module in each time is shown in Figure 4.

The FIR filter modules in the other 7 time blocks are the same as those in Figure 4, except that the signal input data and filter tap coefficients involved in the multiplication operation are different, from x(n-8) to x(n-63) and h(8) to h(63) respectively. After the results of the 8 multiplication and addition modules are sent to the register, the accumulation is completed in the last time block to obtain the final output (relative to the multiplication operation, the time to complete the accumulation can be ignored). The implementation block diagram is shown in Figure 5.
Combining Figures 4 and 5, the FIR filter design based on the LPM parameterized macro function module can be completed. It can be found from the two figures that there are multiple full adders, and the number of bits (bits) of the input data is different. The design can be easily completed by adjusting the parameters of the LPM macro function module. The number of bits of the output data y(n) is based on the high 12 bits of the final accumulation result according to the project needs. The error caused by taking the high 12 bits is (the highest bit is the sign bit, which is not considered numerically), which is an acceptable error.

2 FIR filter design based on Matlab and QuartusⅡ
2.1 Design of filter coefficients using Matlab Design
indicators: sampling frequency is 2 MHz, f1=200 kHz, f2=330 kHz, passband attenuation is 1 dB, stopband attenuation is 70 dB. The required order and parameter values ​​are determined by parameter indicators. Part of the procedure is as follows:

The design indicators are verified by Figure 6.

If the design index is not met, the filter parameters can be adjusted until the design requirements are met.
2.2 Design and simulation using QuartusⅡ
The FIR filter tap coefficients generated by Matlab are simulated using QuartusⅡ. QuartusⅡ software is the main FGPA design software promoted by Altera. It is a design software that integrates design input, compilation, synthesis, simulation, wiring, and downloading. Since the filter tap coefficients generated by Matlab are decimals, they are converted into 18-bit binary coefficients for use according to engineering needs. The process is as follows:
The FIR digital filter coefficients generated by Matlab are as follows:

The design of the FIR filter is completed in QuartusⅡ according to the method proposed in Section 2.3, and the design file is compiled and synthesized through the compilation and synthesis function, and then the top-level module is generated, as shown in Figure 7.

Through the waveform simulation function of QuartusⅡ, the waveform is simulated and quantitatively analyzed. The waveform simulation is shown in Figure 8. Among them, cp50 is the system clock, which controls the input rate of the input signal xin_data (2 MHz in this case). data_result is the multiplication and addition result of the filter without high-order processing; data_result_out is the final filter output result. It has been verified that data_result is consistent with the calculation result of Matlab, and data_result can meet the requirements of engineering accuracy.

3 Conclusion
This paper has completed a FIR filter design based on LPM parameterized macro function module based on Matlab and FPGA software QuartusⅡ. This method is proposed based on practical engineering applications. It does not require high signal processing rate, but has a high order of filter. When the design index changes, only the parameters of each module need to be adjusted to complete the new design. This method has been applied in practical engineering.