An improved method for implementing time division multiple access

With the development of modern communication technology, various multiple access technologies are becoming more and more widely used in daily life. The so-called multiple access technology refers to many users using the same spectrum at the same time, using different processing technologies, so that different user signals can be received and demodulated separately without interfering with each other. Multiple access technology is divided into frequency division multiple access (FDMA), code division multiple access (CDMA), and time division multiple access (TDM-A). Frequency division multiple access is to achieve communication through different frequency channels, code division multiple access is to achieve communication through different code sequences, and time division multiple access is to achieve communication through different time slots. It is a common technology for achieving shared transmission media or networks.

Time division multiple access technology divides time into periodic frames, and each frame is divided into several time slots to send signals through the medium or network. Under the conditions of timing and synchronization, the receiver can receive the corresponding signal in each time slot without interference. Time division multiple access technology has the characteristics of high confidentiality and large transmission capacity.

At present, there are many methods to use FPGA to realize the time division multiple access frame format of multiple signals for transmission, but most of them use a large number of gate circuits in FPGA chips to form registers to realize time division multiple access. This type of method will occupy a large amount of FIGA resources, resulting in a significant reduction in the functions that can be realized by a single FPGA, increasing the engineering cost, and even for some FPGA chips with less resources, this type of method cannot realize time division multiple access transmission. This paper proposes a method based on IP core to realize time division multiple access, using the Block Select RAM Resource (BRAM) inside the chip to store data, saving a large amount of logic gate resources, so that a single FPGA chip can complete more logic functions.

1 Theoretical Analysis

1.1 IP Core

IP core (Intellectual Property core) is a hardware description language program with specific circuit functions. This program is independent of the process of integrated circuits and can be transplanted to different semiconductor processes to produce basic circuit chips. Using IP cores to design electronic systems is convenient for reference and easy to modify the functions of basic components. IP core modules have three different levels of design: behavior, structure, and physical. They are divided into three categories corresponding to the different descriptions of functional behaviors, namely soft cores, solid cores that complete structural descriptions, and hard cores based on descriptions and verified by processes.

1.2 BRAM (Block SeleetRAM Resource)

The types of resources inside FPGA are relatively complex, mainly including the following parts: Input/Output Blocks (IOB), Configurable Logic Blocks (CLB), Block SelectRAM, Multiplier, Digital Clock Management Unit (DCM), Routing Resources, etc. The algorithm proposed in this paper uses the Block SelectRAM integrated inside the chip to realize the transmission of time division multiple access, thereby saving a large number of CLBs, so that the single-chip FPGA can complete more functions.

Each BRAM integrated inside the FPGA chip is a physical dual-port random access memory (dual-port RAM). It has two completely independent sets of data lines, address lines, and read-write control lines, and allows two independent systems to randomly access the memory at the same time, that is, a shared multi-port memory.

The biggest feature of dual-port RAM is the storage data sharing. A memory is equipped with two independent sets of address, data and control lines, allowing two independent controllers to access the storage unit asynchronously at the same time. Because of data sharing, access arbitration control must exist. The internal arbitration logic control provides the following functions: timing control of access to the same address unit; access rights allocation of storage unit data blocks; signaling exchange logic, etc.

The operation of BRAM is similar to that of registers. Control signals, address signals, and input and output data signals must remain valid within the setup time of the clock edge. BRAM will perform read and write operations in this clock cycle to output results or write data. There are three read and write modes: read and write addresses, read-only, and write-only.

1.3 Algorithm Implementation

Step 1: Instantiate the IP core of the dual-port RAM and map the input and output of the program with the input and output of the dual-port RAM.

Step 2: Store the input signal into the RAM through the first set of ports of the dual-port RAM, and read the data stored in the RAM through the second set of ports of the dual-port RAM.

Take 4 signals as an example. Assuming that the sampling rate of each input signal is 48 kHz and the sampling bit number is 64 bits, the bit clock of each input signal is 3.072 MHz. In the first 48 kHz sampling cycle, when the falling edge of the 3.072 MHz bit clock is sampled, the input address is incremented by 1. Then, at the rising edge of the next bit clock, according to the instantiated dual-port RAM IP core, the 4 input data will be stored in the memory address corresponding to the current input address of the dual-port RAM, waiting to be read. Since there are 4 signals in total, that is, the input signal width is 4 bits, the data width stored in the dual-port RAM should also be 4 bits, where the first bit of the stored data in each address corresponds to the first input signal, the second bit corresponds to the second input signal, and so on. The size of the dual-port RAM required at this time is 64x4 bits.

In the next 48 kHz cycle, similar to the previous one, the 4-bit input data will continue to be stored in the new 64 4-bit storage spaces of the dual-port RAM. At the same time, the first 64 4-bit data stored in the previous 48 kHz cycle should be read out and prepared to be transmitted in time division multiple access format.

Step 3: Transmit the data read from the second set of ports in a time division multiple access frame format.

In order to transmit 4-way input signals in a time-division multiplexing format, the 48 kHz time period should be divided into 4 time periods, and the data stored in the dual-port RAM should be read once in each divided time period. First, the first bit of the 64 4-bit data read out should be sent to the time-division multiplexing output in the first divided time period, and then return to the starting address, and read out 64 4-bit data again in the second divided time period, and send the second bit of the data to the time-division multiplexing output, and so on, until all 4-way data are output. Since the data in the dual-port RAM needs to be read repeatedly 4 times in a 48 kHz cycle, the frequency of the bit clock should be increased to 4 times the original frequency, so the bit clock frequency of the read data should be 12.288 MHz.

In the next 48 kHz cycle, the data in the last 64 4-bit storage spaces in the dual-port RAM are sent out in the same way as above. At the same time, since the data in the first 64 4-bit storage spaces have been sent out and no longer need to be saved, the newly input data can be stored in the first 64 4-bit storage spaces. Similarly, the first 64 4-bit storage spaces and the last 64 storage spaces alternately store input data and send out the stored data alternately.

From this we can see that the required dual-port RAM size should be 2x64×4 bits, data is written at port A and read at port B.

2 FPGA Implementation

The FPGA used in the experiment is the XC3SS00E chip in the SPARTAN 3E series of XILINX. The package of the chip is PQ208, the chip speed is -5, the program development language used is VHDL, the synthesis tool is ISE 10.1 of Xilinx, and the simulation tool is ModelSim se 6.2.

Corresponding to the theoretical algorithm, the VHDL program implemented in hardware includes the following modules.

Using the IP core of the dual-port RAM inside the chip, by instantiating the IP core, and taking advantage of the two sets of read and write addresses of a dual-port RAM, the input and output of the program are mapped to the input and output of the dual-port RAM. The internal circuit connects the input and output of the program to the input and output of the dual-port RAM. The operation of the input and output pins of the program is equivalent to the operation of the dual-port RAM. Figure 1 is the register transfer level circuit diagram after the VHDL code of the dual-port RAM is synthesized in Xilinx ISE.

Figure 1 Register transfer level circuit of dual-port RAM

At each falling edge of port A input clock clk3072, port A input address AddrIn is incremented by 1. Then at the rising edge of elk3072, according to the instantiated dual-port RAM IP core, the four input data of port A will be stored in the corresponding address space.

At each falling edge of the port B input clock elk12288, the port B input address AddrOut is incremented by 1. Then, at the rising edge of elk12288, according to the instantiated dual-port RAM IP core, the data in the corresponding address space will be read out through Dout.

The output data is transmitted in sequence in a time division multiple access frame format.

3 Simulation Results

The program is simulated with ModelSim se 6.2b. In the 48 kHz clock cycle, the 64-bit input signal to the first input source is 0x111111111111111111, the 64-bit input signal to the second input source is 0x22222222222222222, the 64-bit input signal to the third input source is 0x3333333333333333, and the 64-bit input signal to the fourth input source is 0x4444444444 444444. The simulation results are shown in Figure 2.

Figure 2 Simulation results

It can be seen from the simulation diagram that in a 48 kHz clock cycle, TDMA_OUT, that is, the output of the time division multiple access frame format is 0x111111111111111122222222222222222223333333 33333333333444444444444444444, that is, each frame is divided into 4 time slots, and the 4 input signals occupy their respective time slots for transmission in each frame. The simulation results can verify the feasibility of this method.

The VHDL language program was synthesized by ISE10.1, and after layout and routing, it was downloaded to XC3S500E through JTAG cable for testing on the circuit board, which once again verified the correctness of this method.

After ISE synthesis, you can see that the chip resources occupied by the program are shown in the following table.

Table 1 Chip resources

From the data in the table, we can see that a lot of resources are saved by using a BRAM. Slices, an important indicator of FPGA chip resources, only occupy 15, and LUTs only occupy 29. It can be seen that this method occupies very few FPGA resources and achieves the design goal.

4 Conclusion

This paper studies an improved method for implementing time division multiple access in FPGA. By using the dual-port RAM inside the FPGA chip and the IP core, multiple signals are converted into time division multiple access frame format signals for transmission. According to the statistical data of occupied resources, it can be seen that under the premise of completing the same function, this method can indeed save a lot of logic resources of the FPGA chip compared with the existing methods, so that the single-chip FPGA can complete more logic functions. However, this method will occupy a part of the dual-port RAM, which is not very applicable when the dual-port RAM resources are tight.

The FPGA program was simulated using ModelSim SE 6.2b and downloaded to the circuit board for verification, which confirmed the feasibility of this method.